Controlling gate length of vertical transistors

Patent metadata

Field	Value
Publication number	US-2020075761-A1
Application number	US-201816114613-A
Country	US
Kind code	A1
Filing date	Aug 28, 2018
Priority date	Aug 28, 2018
Publication date	Mar 5, 2020
Grant date	—

Abstract

A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

First claim

1 . A method of fabricating a semiconductor device, the method comprising:
forming a fin hardmask on an upper surface of a semiconductor substrate; forming a semiconductor fin below the fin hard mask on the upper surface of the semiconductor substrate; selectively depositing first dielectric material on the fin hardmask such that at least one extension portion extends below the upper fin surface to define the length of a channel region of the semiconductor fin that extends between the at least one dielectric material and the semiconductor substrate; selectively depositing a second dielectric material on the first dielectric material such that a second extension portion extends below the at least one extension portion of the first dielectric material; and forming a gate structure on the channel region.

2 . The method of claim 1 , wherein selectively depositing the at least one dielectric material comprises:
performing a first dielectric material deposition process to deposit a first dielectric material that chemically bonds to the fin hardmask; performing a first number of deposition cycles of the first dielectric material deposition process to form a dielectric liner including a liner extension portion that extends below the fin hardmask and the fin upper surface at a first distance; performing a second dielectric material deposition process to deposit a second dielectric material that chemically bonds to the dielectric liner; and performing a second number of deposition cycles of the second dielectric material deposition process to form a top spacer that includes a spacer extension portion that extends below the liner extension portion at a second distance.

3 . The method of claim 2 further comprising defining a gate length of the gate structure based at least in part on a combination of the first distance and the second distance.

4 . The method of claim 3 , wherein the first dielectric material does not chemically bond to a semiconductor material.

5 . The method of claim 4 , wherein the second dielectric material does not chemically bond to a semiconductor material.

6 . The method of claim 5 further comprising forming the liner extension portion so as to define a first tapered profile, and depositing the second dielectric material on the liner extension portion such that the spacer extension portion has a second tapered profile.

7 . The method of claim 6 , wherein forming the gate structure further comprises forming an upper gate portion of the gate structure directly against the liner extension portion such that the upper gate portion has a third tapered profile.

8 . A method of controlling a gate length of a vertical field effect transistor (VFET), the method comprising:
forming a plurality of semiconductor fins on a semiconductor substrate, each semiconductor fin including a lower portion on an upper surface of the semiconductor substrate: forming a bottom source/drain region on the semiconductor substrate, the bottom source/drain region contacting the lower portion of the semiconductor fins; forming a bottom spacer on an upper surface of the bottom source/drain region; selectively depositing first dielectric material on each fin hardmask, and selectively depositing a second dielectric material on the first dielectric material of each semiconductor fin; and forming a gate structure on an exposed channel region to define a gate length of the gate structure.

9 . The method of claim 8 , wherein the gate length of each gate structure is equal to one another.

10 . The method of claim 9 , wherein selectively depositing the at least one dielectric material comprises:
performing a first dielectric material deposition process to deposit the first dielectric material that chemically bonds to the fin hardmask; performing a first number of deposition cycles of the first dielectric material deposition process to form a dielectric liner including a liner extension portion that extends below the fin hardmask and the fin upper surface at a first distance; performing a second dielectric material deposition process to deposit the second dielectric material that chemically bonds to the dielectric liner; and performing a second number of deposition cycles of the second dielectric material deposition process to form a top spacer that includes a spacer extension portion that extends below the liner extension portion at a second distance.

11 . The method of claim 10 , wherein the first number of deposition cycles applied to each semiconductor among the plurality of semiconductor fins is the same, and wherein the second number of deposition cycles applied to each semiconductor among the plurality of semiconductor fins is the same.

12 . The method of claim 11 , wherein the gate length extends between a lower portion of the top spacer and an upper surface of the bottom spacer.

13 . The method of claim 12 further comprising forming the liner extension portion so as to define a first tapered profile, and depositing the second dielectric material on the liner extension portion such that the spacer extension portion has a second tapered profile.

14 . The method of claim 13 , wherein forming the gate structure further comprises forming an upper gate portion of the gate structure directly against the liner extension portion such that the upper gate portion has a third tapered profile

15 . A semiconductor device comprising:
a semiconductor fin extending from a first source/drain to an opposing second source/drain, the semiconductor fin including a channel region between the first and second source/drains; a spacer including an upper surface having the second source/drain formed thereon; and a gate structure wrapping around the channel region, the gate structure including a tapered portion that contacts the spacer.

16 . The semiconductor device of claim 15 , wherein the first source/drain is on a semiconductor substrate, and the semiconductor fin separates the second source/drain from the semiconductor substrate.

17 . The semiconductor device of claim 16 , wherein the spacer includes a tapered lower portion that contacts the tapered portion of the gate structure.

18 . The semiconductor device of claim 17 , wherein the gate structure includes a tapered high-k dielectric (high-k) layer interposed between the tapered portion of the gate structure and the tapered lower portion of the spacer.

19 . The semiconductor device of claim 18 , wherein the gate structure comprises at least one work function metal including an upper tapered portion formed against the tapered high k layer.

20 . The semiconductor device of claim 19 , wherein the upper tapered portion becomes narrower as it extends from sidewalls of the gate structure toward the semiconductor fin.

Assignees

• IBM

Inventors

• Joseph Praveen
• Seshadri Indira
• De Silva Ekmini A
• Sieg Stuart A

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H01L21/76829

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic