Trench junction field effect transistor having a mesa region
US-12550387-B2 · Feb 10, 2026 · US
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Riegler Andreas patents
Riegler Andreas is listed as an inventor on 60 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Riegler Andreas |
| Total patents | 60 |
| First publication | May 19, 2016 |
| Latest publication | Feb 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Semiconductor package including a high voltage semiconductor transistor chip and a dielectric inorganic substrate
US-2026011613-A1 · Jan 8, 2026 · US
Superjunction transistor device
US-12490485-B2 · Dec 2, 2025 · US
Chip-substrate composite semiconductor device
US-2025329545-A1 · Oct 23, 2025 · US
Semiconductor package including a chip-substrate composite semiconductor device
US-12424501-B2 · Sep 23, 2025 · US
Chip-substrate composite semiconductor device
US-12368052-B2 · Jul 22, 2025 · US
Semiconductor device including a trench structure having a trench dielectric structure with a gap
US-12349401-B2 · Jul 1, 2025 · US
Electronic circuit with a transistor device and a biasing circuit
US-12166483-B2 · Dec 10, 2024 · US
Multi-die-package and method
US-12014973-B2 · Jun 18, 2024 · US
Semiconductor device package comprising side walls connected with contact pads of a semiconductor die
US-11978693-B2 · May 7, 2024 · US
Recent patents
Latest publications not already listed above.
Trench junction field effect transistor having a mesa region
US-2023261117-A1 · Aug 17, 2023 · US
Electronic circuit having a transistor device and a biasing circuit
US-11728790-B2 · Aug 15, 2023 · US
Semiconductor package including a chip-substrate composite semiconductor device
US-2023238294-A1 · Jul 27, 2023 · US
Chip-substrate composite semiconductor device
US-2023238333-A1 · Jul 27, 2023 · US
Superjunction Transistor Device
US-2023126534-A1 · Apr 27, 2023 · US
Electronic Circuit with a Transistor Device and a Biasing Circuit
US-2023075897-A1 · Mar 9, 2023 · US
Methods for manufacturing a MOSFET
US-11545561-B2 · Jan 3, 2023 · US
Systems and method for selling content over a network
US-11538008-B2 · Dec 27, 2022 · US
Semiconductor oxide or glass based connection body with wiring structure
US-11527468-B2 · Dec 13, 2022 · US
Semiconductor device including a trench strucure
US-2022310838-A1 · Sep 29, 2022 · US
Electronic circuit having a transistor device and a biasing circuit
US-2022231671-A1 · Jul 21, 2022 · US
Electronic circuit with a transistor device and a biasing circuit
US-11323099-B2 · May 3, 2022 · US
Superjunction transistor device with soft switching behavior
US-11289597-B2 · Mar 29, 2022 · US
Electronic circuit with a transistor device and a biasing circuit
US-2022077845-A1 · Mar 10, 2022 · US
Semiconductor Device Package Comprising Side Walls Connected with Contact Pads of a Semiconductor Die
US-2022037240-A1 · Feb 3, 2022 · US
Chip-substrate composite semiconductor device
US-2022028699-A1 · Jan 27, 2022 · US
Multi-Die-Package and Method
US-2021335696-A1 · Oct 28, 2021 · US
Systems and methods for selling content over a network
US-2021319419-A1 · Oct 14, 2021 · US
Method for operating a superjunction transistor device
US-11088275-B2 · Aug 10, 2021 · US
Multi-die-package and method
US-11081430-B2 · Aug 3, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Infineon Technologies Austria Ag | 39 |
| Infineon Technologies Ag | 14 |
| Intel Corp | 6 |
| Tahoe Res Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D62/111 | 16 |
| H10D62/393 | 14 |
| H10D62/8325 | 14 |
| H10D30/668 | 14 |
| H10W20/081 | 12 |