Superjunction transistor device with soft switching behavior

Patent metadata

Field	Value
Publication number	US-11289597-B2
Application number	US-202016998025-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Aug 22, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A transistor device is enclosed. The transistor device includes: a semiconductor body; a plurality of drift regions of a first doping type; a plurality of compensation regions of a second doping type adjoining the drift regions; and a plurality of transistor cells each including a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The source regions of the plurality of transistor cells are connected to a source node, the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and the plurality of compensation regions are ohmically connected to the source node.

First claim

What is claimed is:

1. A transistor device, comprising:
a semiconductor body;
a plurality of drift regions of a first doping type;
a plurality of compensation regions of a second doping type adjoining the drift regions; and
a plurality of transistor cells each comprising a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric,
wherein the source regions of the plurality of transistor cells are connected to a source node,
wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and
wherein the plurality of compensation regions are ohmically connected to the source node,
wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions by semiconductor regions of a doping type complementary to the doping type of the body regions and the compensation regions.

2. The transistor device of claim 1 , wherein the gate electrodes and the gate dielectrics of the plurality of transistor cells are arranged in gate trenches of the semiconductor body.

3. The transistor device of claim 1 , further comprising:
a source metallization arranged above a first surface of the semiconductor body,
wherein the source metallization:
is connected to the source node or forms the source node;
is connected to each of the source regions of the plurality of transistor cells through at least one first contact plug; and
is connected to each of the plurality of compensation regions through at least one second contact plug.

4. The transistor device of claim 3 , wherein the source metallization is connected to each of the plurality of compensation regions through a plurality of second contact plugs that are spaced apart from each other.

5. The transistor device of claim 4 , wherein each of the compensation regions has a dimension in a vertical direction of the semiconductor body, and wherein a distance between two neighboring second contact plugs of the plurality of second contact plugs is between 0.1 times and 10 times the vertical dimension of the respective compensation region.

6. The transistor device of claim 4 , wherein a distance between two neighboring second contact plugs of the plurality of second contact plugs is greater than 10 micrometers.

7. The transistor device of claim 4 , further comprising:
a plurality of intermediate regions of the second doping type,
wherein each of the plurality of intermediate regions is arranged between a respective one of the plurality of second contact plugs and the respective compensation region,
wherein a doping concentration of each of the plurality of intermediate regions is higher than a doping concentration of the respective compensation region, and
wherein the plurality of intermediate regions are spaced apart from each other.

8. The transistor device of claim 7 , wherein each of the compensation regions has a dimension in a vertical direction of the semiconductor body, and wherein a distance between two neighboring intermediate regions of the plurality of intermediate regions is between 0.1 times and 10 times the vertical dimension of the respective compensation region.

9. The transistor device of claim 1 , wherein an overall cross sectional area of the first contact plugs is greater than an overall cross sectional area of the second contact plugs.

10. The transistor device of claim 1 , wherein the plurality of compensation regions and the body regions of the plurality of transistor cells are elongated in a first lateral direction of the semiconductor body and parallel to each other.

11. The transistor device of claim 1 , further comprising:
a drain region coupled to the plurality of drift regions.

12. The transistor device of claim 11 , wherein the drain region is spaced apart from the transistor cells in a vertical direction of the semiconductor body.

13. A transistor device, comprising:
a semiconductor body;
a plurality of drift regions of a first doping type;
a plurality of compensation regions of a second doping type adjoining the drift regions;
a plurality of transistor cells each comprising a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and
a source metallization arranged above a first surface of the semiconductor body,
wherein the source regions of the plurality of transistor cells are connected to a source node,
wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body,
wherein the plurality of compensation regions are ohmically connected to the source node,
wherein the source metallization is connected to the source node or forms the source node, is connected to each of the source regions of the plurality of transistor cells through at least one first contact plug, and is connected to each of the plurality of compensation regions through a plurality of second contact plugs that are spaced apart from each other,
wherein each of the compensation regions has a dimension in a vertical direction of the semiconductor body,
wherein a distance between two neighboring second contact plugs of the plurality of second contact plugs is between 0.1 times and 10 times the vertical dimension of the respective compensation region.

14. The transistor device of claim 13 , wherein the gate electrodes and the gate dielectrics of the plurality of transistor cells are arranged in gate trenches of the semiconductor body, and wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions by the gate trenches.

15. The transistor device of claim 13 , wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions by trenches in the semiconductor body that have at least their surfaces covered with an insulator.

16. A transistor device, comprising:
a semiconductor body;
a plurality of drift regions of a first doping type;
a plurality of compensation regions of a second doping type adjoining the drift regions;
a plurality of transistor cells each comprising a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and
a source metallization arranged above a first surface of the semiconductor body,
wherein the source regions of the plurality of transistor cells are connected to a source node,
wherein the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and
wherein the plurality of compensation regions are ohmically connected to the source node,
wherein the source metallization is connected to the source node or forms the source node, is connected to each of the source regions of the plurality of transistor cells through at least one first contact plug, and is connected to each of the plurality of compensation regions through a plurality of second contact plugs that are spaced apart from each other,
wherein a distance between two neighboring second contact plugs of the plurality of second contact plu

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Fischer Björn
• Hirler Franz
• Kutschak Matteo-Alessandro
• Riegler Andreas

Classifications

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title