Multi-die-package and method

Patent metadata

Field	Value
Publication number	US-11081430-B2
Application number	US-201816193514-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 17, 2017
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A package and a corresponding method are described. The method includes: providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

First claim

What is claimed is:

1. A package enclosing a first power semiconductor die and a second power semiconductor die, the package comprising a package body with a package top side and a package footprint side, wherein:
each of the first power semiconductor die and the second power semiconductor die has a respective front side and, opposite thereof, a respective back side;
the first power semiconductor die has a first load terminal arranged at its front side and a second load terminal arranged at its back side;
the second power semiconductor die has a first load terminal arranged at its front side and a second load terminal arranged at its back side;
the package further comprises a lead frame structure configured to electrically and mechanically couple the package to a support with the package footprint side facing the support; and
the lead frame structure comprises:
a common base, wherein the second load terminal of the first power semiconductor die is electrically connected to the common base with its back side facing the common base, and wherein the first load terminal of the second power semiconductor die is electrically connected to the common base with its front side facing the common base;
a common outside terminal extending out of the package body and being electrically connected with the common base;
a first outside terminal extending out of the package body and being electrically connected with the first load terminal of the first power semiconductor die; and
a second outside terminal extending out of the package body and being electrically connected with the second load terminal of the second power semiconductor die and electrically insulated from the first outside terminal, and
wherein the common base comprises a conductive span that is disposed within the package and extends underneath both of the first and second semiconductor dies.

2. The package of claim 1 , wherein the second load terminal of the first power semiconductor die is one of a drain terminal, a collector terminal and a cathode terminal, and wherein the first load terminal of the second power semiconductor die is one of an anode terminal, a source terminal and an emitter terminal.

3. The package of claim 1 , wherein the first load terminal of the first power semiconductor die is one of a source terminal, an emitter terminal and an anode terminal, and wherein the second load terminal of the second power semiconductor die is one of a cathode terminal, a drain terminal and a collector terminal.

4. The package of claim 1 , wherein the first power semiconductor die further comprises a control terminal at its front side, and wherein the lead frame structure comprises a third outside terminal extending out of the package body, the third outside terminal being electrically connected with the control terminal of the first power semiconductor die.

5. The package of claim 1 , wherein the second load terminal of the first power semiconductor die is arranged in contact with the common base of the lead frame structure, and wherein the first load terminal of the second power semiconductor die is spatially displaced from the common base.

6. The package of claim 1 , wherein the second power semiconductor die forms a part of a stack unit enclosed within the package, wherein the stack unit comprises a monolithic coupling layer arranged between the common base of the lead frame structure and the front side of the second power semiconductor die, wherein the monolithic coupling layer is made of an insulating material and has at least one passage filled with an electrically conductive material, and wherein the at least one passage forms the electrical connection between the first load terminal of the second power semiconductor die and the common base.

7. The package of claim 6 , wherein the monolithic coupling layer provides for a spatial displacement between the common base and the first load terminal of the second power semiconductor die.

8. The package of claim 6 , wherein the insulating material of the monolithic coupling layer is configured with a breakthrough voltage at least as great as a breakthrough voltage of the second power semiconductor die.

9. The package of claim 1 , wherein each of the common outside terminal, the first outside terminal and the second outside terminal is configured for being coupled to the support.

10. The package of claim 1 , wherein each of the first outside terminal and the second outside terminal extend from out of the interior of the package body to external of the package body.

11. The package of claim 1 , wherein the second power semiconductor die includes, at its front side, an active region and an edge termination region surrounding the active region.

12. The package of claim 1 , wherein both the front side of the first power semiconductor die and the back side of the second power semiconductor die face the package top side, or wherein both the front side of the first power semiconductor die and the back side of the second power semiconductor die face to the package footprint side.

13. The package of claim 1 , wherein both the front side of the first power semiconductor die and the back side of the second power semiconductor die face the package footprint side, wherein the package is a top-side-cooling package, and wherein the common base has an exterior surface that forms the cooling top side of the package.

14. A power converter comprising the package of claim 1 , wherein the power converter is configured to receive an input power signal from an input power source, to convert the input power signal into an output power signal and to provide the output power signal for a load.

15. The power converter of claim 14 , wherein the first outside terminal and the second outside terminal are not short-circuited which each other.

16. The package of claim 1 , wherein the first and second semiconductor dies are each mounted on a flat surface of the conductive span that extends along a single plane.

17. The package of claim 1 , wherein the package body is a region of electrically insulating material that encapsulates the first and second power semiconductor dies, and wherein the first outside terminal and the common terminal protrude out of a first sidewall of the package body at locations that are spaced apart from one another in a vertical direction that is perpendicular to the package top side and the package bottom side.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Riegler Andreas
• Fachmann Christian

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W70/461

  specially adapted for cooling · CPC title

• H10W70/427

  Bent parts · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title