Superjunction transistor device

Patent metadata

Field	Value
Publication number	US-12490485-B2
Application number	US-202117792447-A
Country	US
Kind code	B2
Filing date	Jan 19, 2021
Priority date	Jan 20, 2020
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A transistor device is disclosed. The transistor device includes: a semiconductor body ( 100 ); a drift region ( 11 ) in the semiconductor body ( 100 ); a plurality of transistor cells ( 10 ); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells ( 10 ) includes: a first trench electrode ( 21 ) insulated from the semiconductor body ( 100 ) by a first dielectric layer ( 22 ); a second trench electrode ( 23 ) insulated from the semiconductor body ( 100 ) by a second dielectric layer ( 24 ); a source region ( 13 ) and a body region ( 14 ) in a first mesa region ( 111 ) between the first trench electrode ( 21 ) and the second trench electrode ( 23 ); and a compensation region ( 12 ), wherein the compensation region ( 12 ) adjoins the body region ( 14 ), the first dielectric ( 22 ), the second dielectric ( 24 ), and forms a pn-junction with the drift region ( 11 ), and wherein from the first trench electrode ( 21 ) and the second trench electrode ( 23 ) at least the first trench electrode ( 21 ) is connected to the gate node (G).

First claim

The invention claimed is:

1 . A transistor device, comprising:
a semiconductor body; a drift region in the semiconductor body; a plurality of transistor cells; a plurality of second mesa regions each arranged between two neighboring transistor cells and adjoining a first surface of the semiconductor body, wherein at least one of the plurality of second mesa regions comprises a section of the drift region that extends to the first surface; a gate node; and a source node; wherein each of the plurality of transistor cells comprises:
a first trench electrode insulated from the semiconductor body by a first dielectric layer, and connected to the gate node or the source node;
a second trench electrode insulated from the semiconductor body by a second dielectric layer, and connected to the gate node, the source node or is floating;
a source region and a body region in a first mesa region between the first trench electrode and the second trench electrode; and
a compensation region,
wherein the compensation region adjoins the body region, the first dielectric, and the second dielectric, and forms a pn-junction with the drift region,
wherein the plurality of transistor cells comprises a transistor cell type in which the first trench electrode is connected to the source node and the second trench electrode is connected to the source node.

2 . The transistor device of claim 1 , wherein the plurality of transistor cells comprises another transistor cell type in which the first trench electrode is connected to the gate node and the second trench electrode is connected to the gate node.

3 . The transistor device of claim 1 , wherein the plurality of transistor cells comprises another transistor cell type in which the first trench electrode is connected to the gate node and the second trench electrode is connected to the source node.

4 . The transistor device of claim 1 , wherein at least one of the plurality of second mesa regions comprises a doped region that forms a pn-junction with the drift region.

5 . The transistor device of claim 1 , further comprising:
a Schottky contact formed between the source node and the drift region in at least one of the second mesa regions.

6 . The transistor device of claim 1 , further comprising:
a bias node different from the source node, wherein the bias node is connected to the drift region in the plurality of second mesa regions.

7 . The transistor device of claim 1 , further comprising:
a drain region connected to a drain node or forming a drain node of the transistor device.

8 . The transistor device of claim 1 , wherein at least the first dielectric layer comprises a rounded corner in a region where the first dielectric layer adjoins the compensation region.

9 . The transistor device of claim 8 , wherein an inner radius of the rounded corner is between 0.5 times and 3 times of a thickness of the first dielectric layer.

10 . An electronic circuit, comprising:
the transistor device of claim 6 ; and an electronic switch and a bias voltage source connected in series between the source node and the bias node.

11 . A transistor device, comprising:
a semiconductor body; a drift region in the semiconductor body; a plurality of transistor cells; a plurality of second mesa regions each arranged between two neighboring transistor cells and adjoining a first surface of the semiconductor body, wherein at least one of the plurality of second mesa regions comprises a section of the drift region that extends to the first surface; a gate node; and a source node; wherein each of the plurality of transistor cells comprises:
a first trench electrode insulated from the semiconductor body by a first dielectric layer, and connected to the gate node or the source node;
a second trench electrode insulated from the semiconductor body by a second dielectric layer, and connected to the gate node, the source node or is floating;
a source region and a body region in a first mesa region between the first trench electrode and the second trench electrode; and
a compensation region,
wherein the compensation region adjoins the body region, the first dielectric, and the second dielectric, and forms a pn-junction with the drift region,
wherein the plurality of transistor cells comprises a transistor cell type in which the first trench electrode is connected to the gate node and the second trench electrode is connected to the source node.

12 . The transistor device of claim 11 , wherein at least one of the plurality of second mesa regions comprises a doped region that forms a pn-junction with the drift region.

13 . The transistor device of claim 11 , further comprising:
a Schottky contact formed between the source node and the drift region in at least one of the second mesa regions.

14 . The transistor device of claim 11 , further comprising:
a bias node different from the source node, wherein the bias node is connected to the drift region in the plurality of second mesa regions.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Fischer Björn
• Hirler Franz
• Kutschak Matteo-Alessandro
• Riegler Andreas

Classifications

• H10D84/146

  the built-in components being Schottky barrier diodes · CPC title

• H10D84/143

  the built-in components being PN junction diodes · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title