Semiconductor package including a chip-substrate composite semiconductor device

Patent metadata

Field	Value
Publication number	US-12424501-B2
Application number	US-202318099290-A
Country	US
Kind code	B2
Filing date	Jan 20, 2023
Priority date	Jan 21, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.

First claim

What is claimed is:

1. A high voltage semiconductor package, comprising:
a semiconductor device comprising:
a high voltage semiconductor transistor chip comprising a front side and a backside, wherein a low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip and a high voltage load electrode is disposed on the backside of the semiconductor transistor chip;
a dielectric inorganic substrate comprising:
a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode; and
at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode,

wherein the front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and
wherein the dielectric inorganic substrate has a thickness of at least 50 μm.

2. The high voltage semiconductor package of claim 1 , further comprising:
a leadframe comprising a first leadframe pad and a second leadframe pad,
wherein the dielectric inorganic substrate is bonded to the leadframe,
wherein the pattern of first metal structures is bonded to the first leadframe pad and the at least one second metal structure is bonded to the second leadframe pad.

3. The high voltage semiconductor package of claim 2 , wherein the first leadframe pad forms a source terminal of the high voltage semiconductor package and the second leadframe pad forms a gate terminal of the high voltage semiconductor package.

4. The high voltage semiconductor package of claim 2 , further comprising:
an electrically conductive element bonded to the high voltage load electrode of the semiconductor transistor chip and connecting to a high voltage terminal of the high voltage semiconductor package.

5. The high voltage semiconductor package of claim 1 , further comprising:
a laminate structure in which the semiconductor device is embedded.

6. The high voltage semiconductor package of claim 5 , wherein the laminate structure is a printed circuit board.

7. The high voltage semiconductor package of claim 5 , wherein the laminate structure is a core laminate structure, the high voltage semiconductor package further comprising:
a bottom laminate structure extending below the core laminate structure and the semiconductor device; and/or
a top laminate structure extending above the core laminate structure and the semiconductor device.

8. The high voltage semiconductor package of claim 1 , wherein the dielectric inorganic substrate is a glass substrate.

9. The high voltage semiconductor package of claim 8 , wherein the wafer bond connection is a glass frit connection.

10. The high voltage semiconductor package of claim 1 , wherein the first metal structures are connected to the low voltage load electrode by a metal-to-metal wafer bond connection, and/or the at least one second metal structure is connected to the control electrode by a metal-to-metal wafer bond connection.

11. The high voltage semiconductor package of claim 1 , wherein the dielectric inorganic substrate comprises a plurality of stacked dielectric inorganic substrate layers.

12. The high voltage semiconductor package of claim 1 , wherein the first metal structures are plated metal pillars.

13. The high voltage semiconductor package of claim 1 , wherein the pattern is a regular array.

14. The high voltage semiconductor package of claim 1 , wherein a ratio of a distance between adjacent first metal structures and a lateral dimension of a first metal structure is equal to or less than 5 or 3 or 2 or 1.

15. The high voltage semiconductor package of claim 1 , wherein the front side of the semiconductor transistor chip is completely covered by the dielectric inorganic substrate.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Fachmann Christian
• Glanzer Barbara Angela
• Riegler Andreas

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title