Electronic circuit having a transistor device and a biasing circuit

Patent metadata

Field	Value
Publication number	US-11728790-B2
Application number	US-202217712782-A
Country	US
Kind code	B2
Filing date	Apr 4, 2022
Priority date	Sep 7, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

First claim

What is claimed is:

1. An electronic circuit, comprising:
a transistor device comprising a load path and a drive input; and
a biasing circuit connected in parallel with the load path of the transistor device,
wherein the biasing circuit is configured to connect a bias voltage circuit providing a bias voltage to the load path of the transistor device,
wherein the biasing circuit includes at least one inductor,
wherein the transistor device is a superjunction transistor device.

2. The electronic circuit of claim 1 , wherein the transistor device comprises:
a drift region with a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type; and
a control structure connected between a source node of the transistor device and the first regions.

3. The electronic circuit of claim 2 , wherein the control structure comprises a gate node of the transistor device and is configured to control a conducting channel between the source node and the first regions dependent on a drive voltage received between the gate node and the source node.

4. The electronic circuit of claim 2 , wherein the control structure comprises a pn-junction between the first regions and the source node.

5. The electronic circuit of claim 2 , wherein the control structure comprises a plurality of control cells, each control cell comprising a body region of the second doping type, a source region of the first doping type, a gate electrode, and a gate dielectric that dielectrically insulates the gate electrode from the body region.

6. The electronic circuit of claim 5 , wherein the body region of each control cell adjoins at least one first region such that there is a pn-junction between the body region of each control cell and the at least one first region.

7. The electronic circuit of claim 5 , wherein the gate electrode of each control cell is a planar electrode arranged on top of a first surface of a semiconductor body and dielectrically insulated from the semiconductor body by the gate dielectric.

8. The electronic circuit of claim 5 , wherein the gate electrode of each control cell is a trench electrode arranged in a trench that extends from a first surface of a semiconductor body and into the semiconductor body.

9. The electronic circuit of claim 5 , wherein the body region of each control cell adjoins at least one second region such that the at least one second region is electrically connected to the source node via the body region of the control cell.

10. The electronic circuit of claim 5 , wherein the first regions and the second regions are elongated in a second lateral direction of a semiconductor body, and wherein the source regions, the body regions, and the gate electrodes of the individual control cells of the control structure are elongated in a first lateral direction perpendicular to the second lateral direction.

11. The electronic circuit of claim 5 , wherein the body region of one control cell adjoins a plurality of the first regions and a plurality of the second regions.

12. An electronic circuit, comprising:
a superjunction transistor device comprising a drain node and a source node; and
a biasing circuit connected between the drain node and the source node of the transistor device and configured to connect a bias voltage circuit between the drain node and the source node,
wherein the superjunction transistor device further comprises a drift region with a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type,
wherein the first regions are connected to the drain node and the second regions are connected to the source node,
wherein pn-junctions are formed between the first regions and the second regions,
wherein a pitch of the drift region is smaller than 7.5 μm, the pitch corresponding to a center distance between two neighboring first regions or a center distance between two neighboring second regions.

13. The electronic circuit of claim 12 , further comprising:
a drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage.

14. The electronic circuit of claim 13 , wherein the bias voltage equals the supply voltage.

15. The electronic circuit of claim 12 , wherein the bias voltage circuit is configured to receive the supply voltage and generate the bias voltage such that the bias voltage is higher than the supply voltage.

16. The electronic circuit of claim 12 , wherein the biasing circuit includes at least one inductor.

17. The electronic circuit of claim 12 , wherein the superjunction transistor device comprises:
a control structure connected between the source node and the first regions.

18. The electronic circuit of claim 17 , wherein the control structure comprises a gate node of the superjunction transistor device and is configured to control a conducting channel between the source node and the first regions dependent on a drive voltage received between the gate node and the source node.

19. The electronic circuit of claim 17 , wherein the control structure comprises a plurality of control cells, each control cell comprising a body region of the second doping type, a source region of the first doping type, a gate electrode, and a gate dielectric that dielectrically insulates the gate electrode from the body region.

20. The electronic circuit of claim 19 , wherein the body region of each control cell adjoins at least one first region such that there is a pn-junction between the body region of each control cell and the at least one first region.

21. The electronic circuit of claim 19 , wherein the gate electrode of each control cell is a planar electrode arranged on top of a first surface of a semiconductor body and dielectrically insulated from the semiconductor body by the gate dielectric.

22. The electronic circuit of claim 19 , wherein the gate electrode of each control cell is a trench electrode arranged in a trench that extends from a first surface of a semiconductor body and into the semiconductor body.

23. The electronic circuit of claim 19 , wherein the body region of each control cell adjoins at least one second region such that the at least one second region is electrically connected to the source node via the body region of the control cell.

24. The electronic circuit of claim 19 , wherein the first regions and the second regions are elongated in a second lateral direction of a semiconductor body, and wherein the source regions, the body regions, and the gate electrodes of the individual control cells of the control structure are elongated in a first lateral direction perpendicular to the second lateral direction.

25. The electronic circuit of claim 19 , wherein the body region of one control cell adjoins a plurality of the first regions and a plurality of the second regions.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Hirler Franz
• Kutschak Matteo-Alessandro
• Riegler Andreas

Classifications

• H10D62/8325

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• H03K3/012 Primary

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• H01L29/1608

  Electricity · mapped topic

• H02M1/082

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• H02M3/33571

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