Semiconductor oxide or glass based connection body with wiring structure

Patent metadata

Field	Value
Publication number	US-11527468-B2
Application number	US-201916568818-A
Country	US
Kind code	B2
Filing date	Sep 12, 2019
Priority date	Sep 14, 2018
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.

First claim

What is claimed is:

1. A semiconductor device, comprising
a chip carrier comprising a substantially planar mounting surface;
an electronic chip that comprises an upper main surface with a conductive pad and a rear surface opposite the upper main surface;
a connection body that comprises a glass base structure and an electrically conductive wiring structure,
wherein the connection body is mounted on the chip carrier with the glass base structure facing and adhered to the mounting surface,
wherein an enclosed cavity is disposed between the connection body and the chip carrier,
wherein the electronic chip is disposed within the enclosed cavity,
wherein the electrically conductive wiring structure is connected to the conductive pad of the electronic chip,
wherein the electronic chip is mounted on the chip carrier such that the rear surface is flush against the mounting surface,
wherein the chip carrier is an electrically conductive leadframe.

2. The semiconductor device of claim 1 , wherein the wiring structure comprises a conductive track that is electrically connected to the conductive pad, and wherein the conductive track laterally extends across an outer edge side of the electronic chip.

3. The semiconductor device of claim 2 , further comprising an electrically conductive lead that is spaced apart from the chip carrier, wherein the conductive track laterally extends across a gap between the electrically conductive lead and the chip carrier, and wherein the conductive track electrically connects the lead to the conductive pad.

4. The semiconductor device of claim 1 , wherein a portion of the glass base structure directly contacts the electronic chip.

5. The semiconductor device of claim 1 , wherein the glass base structure comprises an outer surface that is opposite from the mounting surface, and wherein the outer surface of the glass base structure forms a complete outer side of the semiconductor device.

6. The semiconductor device of claim 5 , wherein the electrically conductive wiring structure is completely covered by the glass base structure.

7. The semiconductor device of claim 1 , wherein a ratio between a lateral width and a thickness of the electrically conductive wiring structure is at least 5.

8. The semiconductor device of claim 1 , wherein the electronic chip is a semiconductor chip that comprises at least one integrated power transistor.

9. The semiconductor device of claim 1 , wherein the glass base structure comprises a recess that extends from a planar outer surface, wherein the planar outer surface of the glass base structure faces and is adhered to the mounting surface of the chip carrier, and wherein the enclosed cavity is bounded by the recess in the glass base structure and the mounting surface of the chip carrier.

10. The semiconductor device of claim 9 , wherein the electronic chip is spaced apart from the glass base structure.

11. The semiconductor device of claim 1 , wherein the glass base structure is a structure that is at least predominantly made of glass or semiconductor oxide, and wherein the glass or semiconductor oxide extends from inside surface of the glass base structure that faces the planar mounting surface to an outside surface of the glass base structure that faces away from the planar mounting surface.

12. A semiconductor device, comprising
a chip carrier comprising a substantially planar mounting surface;
an electronic chip that comprises an upper main surface with a conductive pad;
a connection body that comprises a glass base structure and an electrically conductive wiring structure,
wherein the connection body is mounted on the chip carrier with the glass base structure facing and adhered to the mounting surface,
wherein an enclosed cavity is disposed between the connection body and the chip carrier,
wherein the electronic chip is disposed within the enclosed cavity,
wherein a conductive track of the electrically conductive wiring structure is disposed directly over the upper main surface and electrically contacts the conductive pad,
wherein the chip carrier is an electrically conductive leadframe.

13. The semiconductor device of claim 12 , wherein the electrically conductive wiring structure is completely disposed above the upper main surface of the electronic chip.

14. The semiconductor device of claim 12 , wherein the conductive track directly contacts the glass base structure.

15. The semiconductor device of claim 12 , wherein the chip carrier comprises a mounting section and a plurality of lead sections that are spaced apart from the mounting section, and wherein the electronic chip is mounted on the mounting section.

16. The semiconductor device of claim 15 , wherein the mounting section and the lead sections are monolithic portions of an electrically conductive lead frame.

17. The semiconductor device of claim 12 , wherein the glass base structure comprises a recess that extends from a planar outer surface, wherein the planar outer surface of the glass base structure faces and is adhered to the mounting surface of the chip carrier, and wherein the enclosed cavity is bounded by the recess in the glass base structure and the mounting surface of the chip carrier.

18. The semiconductor device of claim 12 , wherein the electronic chip is spaced apart from the glass base structure.

19. The semiconductor device of claim 12 , wherein the glass base structure is a structure that is at least predominantly made of glass or semiconductor oxide, and wherein the glass or semiconductor oxide extends from inside surface of the glass base structure that faces the planar mounting surface to an outside surface of the glass base structure that faces away from the planar mounting surface.

Assignees

• Infineon Technologies Ag

Inventors

• Riegler Andreas
• Fachmann Christian
• Kutschak Matteo-Alessandro
• Von Koblinski Carsten
• Weber Hans

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title