Chip-substrate composite semiconductor device

Patent metadata

Field	Value
Publication number	US-12368052-B2
Application number	US-202117380067-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	Jul 21, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer, wherein the metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer, and wherein the metal structures protrude from a first surface and a second surface of the dielectric inorganic substrate wafer;
providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer;
bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is directly connected to the plurality of electrodes; and
separating the composite wafer into composite chips, at least one of the composite chips comprising one or more package terminals each implemented as a pattern of at least two distinct and separated metal structures protruding from an outer surface of the composite chip,
wherein at least one of the plurality of patterns of metal structures includes adjacent metal structures that are spaced apart from each other by a distance equal to or less than 10 μm or 5 μm or 4 μm or 3 μm and/or a pitch that is equal to or less than 15 μm or 17.5 μm or 20 μm or 27.5 μm or 30 μm.

2. The method of claim 1 , wherein forming a plurality of patterns of metal structures in the dielectric inorganic substrate wafer comprises:
forming recesses in the first surface of the dielectric inorganic substrate wafer;
metal plating to fill the recesses with metal; and
thinning the dielectric inorganic substrate wafer from the second surface opposite the first surface to expose the metal of at least a part of the recesses,
wherein sidewalls of the metal filling the recesses protrude from the first surface and the second surface of the dielectric inorganic substrate wafer.

3. The method of claim 2 , wherein the thinning comprises:
grinding the dielectric inorganic substrate wafer down to a thickness which is larger than the depth of the recesses; and
etching the dielectric inorganic substrate wafer to expose the metal.

4. The method of claim 1 , wherein bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer comprises:
applying a kerf pattern of bonding material between the semiconductor wafer and the dielectric inorganic substrate wafer; and
applying heat and pressure to bond the semiconductor wafer to the dielectric inorganic substrate wafer, thereby connecting the plurality of electrodes to the plurality of patterns of metal structures.

5. The semiconductor device of claim 4 , wherein the plurality of electrodes is connected to the plurality of patterns of metal structures by solder-free connections.

6. The method of claim 1 , wherein a percentage in volume of metal in the dielectric inorganic substrate wafer within a pattern of metal structures is equal to or greater than 60% or 70% or 80%.

7. The method of claim 1 , wherein the metal structures in at least one of the plurality of patterns of metal structures have a rounded or a polygonal cross-sectional shape.

8. The method of claim 7 , wherein the cross-sectional shape of the metal structures is hexagonal.

9. The method of claim 1 , wherein at least one of the plurality of patterns of metal structures includes a plurality of different patterns of metal structures.

10. The method of claim 1 , wherein at least one of the plurality of patterns of metal structures is a regular array.

11. The method of claim 1 , wherein forming the plurality of patterns of metal structures in the dielectric inorganic substrate wafer comprises:
forming at least one densely packed array of the metal structures in the dielectric inorganic substrate wafer, wherein adjacent metal structures in the densely packed array are spaced apart from each other by a distance equal to or less than 10 μm or 5 μm or 4 μm or 3 μm.

12. The method of claim 11 , wherein the at least one densely packed array of the metal structures includes a pitch that is equal to or less than 15 μm or 17.5 μm or 20 μm or 27.5 μm or 30 μm.

13. The method of claim 11 , wherein the at least one densely packed array of the metal structures includes a pattern of metal structures having a plurality of different patterns.

14. The method of claim 11 , wherein the at least one densely packed array of the metal structures includes a pattern of metal structures having a regular array.

15. The method of claim 11 , wherein the cross-sectional shape of the metal structures in the at least one densely packed array is hexagonal.

16. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer, wherein the metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer, and wherein the metal structures protrude from a first surface and a second surface of the dielectric inorganic substrate wafer;
providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer;
bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is directly connected to the plurality of electrodes; and
separating the composite wafer into composite chips, wherein distinct and separated portions of individual metal structures that protrude from the dielectric inorganic substrate wafer form one or more package terminals of the composite chips,
wherein at least one of the plurality of patterns of metal structures includes adjacent metal structures that are spaced apart from each other by a distance equal to or less than 10 μm or 5 μm or 4 μm or 3 μm and/or a pitch that is equal to or less than 15 μm or 17.5 μm or 20 μm or 27.5 μm or 30 μm.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer, wherein the metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate wafer, and wherein the metal structures protrude from a first surface and a second surface of the dielectric inorganic substrate wafer;
providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer;
bonding the front side of the semiconductor wafer to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is directly connected to the plurality of electrodes; and
separating the composite wafer into composite chips,
wherein at least one of the plurality of patterns of metal structures includes adjacent metal structures that are spaced apart from each other by a distance equal to or less than 10 μm or 5 μm or 4 μm or 3 μm and/or a pitch that is equal to or less than 15 μm or 17.5 μm or 20 μm or 27.5 μm or 30 μm, and
wherein a percentage in volume of metal in the dielectric inorganic substrate wafer within a pattern of metal structures is equal to or greater than 60% or 7

Assignees

• Infineon Technologies Austria Ag

Inventors

• Fachmann Christian
• Glanzer Barbara Angela
• Riegler Andreas

Classifications

• H10P95/60

  Mechanical treatments, e.g. by ultrasounds · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title