Methods for manufacturing a MOSFET

Patent metadata

Field	Value
Publication number	US-11545561-B2
Application number	US-202017134627-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Sep 11, 2017
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

First claim

The invention claimed is:

1. A MOSFET, comprising:
a semiconductor body comprising a first side, a drift region adjacent to the first side, a body region adjacent to the first side and forming a first pn-junction with the drift region, and a source region adjacent to the first side and forming a second pn-junction with the body region;

in a vertical cross-section perpendicular to the first side, the MOSFET further comprises:
a dielectric structure arranged on the first side and having an upper side;
a first gate electrode;
a second gate electrode;
a contact trench arranged between the first gate electrode and the second gate electrode, extending through the dielectric structure and at least to the source region, wherein in a horizontal direction a width of the contact trench has, in a first plane defined by the first side, a first value, and, in a second plane defined by the upper side, a second value which is at most about 2.5 times the first value; and
a first contact structure arranged on the dielectric structure and comprising a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

2. The MOSFET of claim 1 , wherein, the second value is at most about 1 μm, wherein a vertical distance between the first side and the upper side decreases with increasing horizontal distance from a sidewall of the contact trench and/or from the through contact portion, wherein a vertical distance of an upper end of the sidewall from the first side is larger than a minimum vertical distance between the first side and the upper side, wherein the vertical distance of the upper end of the sidewall from the first side is at most about 100 nm larger than the minimum vertical distance between the first side and the upper side, and/or wherein the vertical distance has a lowest value at a value of the horizontal distance which is lower than a maximum distance of the source region in a projection onto the first side, wherein the vertical distance only decreases for values of the horizontal distance which are smaller than about 70 nm.

3. The MOSFET of claim 1 , wherein the MOSFET comprises in the vertical cross-section a plurality of MOSFET-cells each comprising a respective contact trench arranged between two adjacent gate electrodes, and extending through the dielectric structure and at least to a respective source region, wherein the MOSFET is implemented as a power semiconductor device, and/or wherein the MOSFET is implemented as a compensation semiconductor device.

4. The MOSFET of claim 1 , wherein, in the vertical cross-section, a transition region between the sidewall and the upper side and/or a surface of the contact structure in a transition region between the through contact portion and a covering portion of the first contact structure has a parametric plane curve comprising a cusp.

5. The MOSFET of claim 1 , wherein the drift region comprises dopants of the n-type and/or recombination centers for holes.

6. The MOSFET of claim 1 , wherein the first and second gate electrodes are each embedded in the dielectric structure comprises.

7. The MOSFET of claim 6 , wherein, in the vertical cross-section, the dielectric structure comprises:
a first gate dielectric portion arranged between the first gate electrode and the first side;
a second gate dielectric portion arranged between the second gate electrode and the first side;
a lower dielectric layer arranged at the first gate electrode and the second gate electrode;
an upper dielectric layer arranged on the lower dielectric layer; and/or
a sidewall dielectric arranged at the sidewall and having a layer thickness of at most about 10 nm.

8. The MOSFET of claim 1 , wherein, in the vertical cross-section, the first contact structure comprises:
a lower conductive layer forming an interface with the dielectric structure at the upper side;
an intermediate conductive layer arranged on the lower conductive layer; and/or
an upper conductive layer arranged on the intermediate conductive layer.

9. The MOSFET of claim 8 , wherein the lower conductive layer comprises titanium, wherein the intermediate conductive layer comprises tungsten, and wherein the upper conductive layer comprises an alloy comprising at least one of aluminum, copper and silicon.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Riegler Andreas
• Jantscher Wolfgang
• Pippan Manfred
• Stegemann Maik

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title