Method for operating a superjunction transistor device

Patent metadata

Field	Value
Publication number	US-11088275-B2
Application number	US-202016811492-A
Country	US
Kind code	B2
Filing date	Mar 6, 2020
Priority date	Mar 8, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.

First claim

What is claimed is:

1. A method, comprising:
operating a superjunction transistor device in a diode state,
wherein operating the superjunction transistor device in the diode state comprises applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region,
wherein the compensation region adjoins the drift region,
wherein a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.

2. The method of claim 1 , wherein the compensation region is spaced apart from a body region of the at least one transistor cell, and wherein the bias voltage is applied between the compensation region and the body region.

3. The method of claim 1 , wherein the compensation region adjoins the body region of the at least one transistor cell, wherein the bias voltage is applied between the compensation region and a bias region, and wherein the bias region is of a same doping type as the compensation region, adjoins the drift region and is spaced apart from the body region.

4. The method of claim 1 , wherein operating the superjunction transistor device in the diode state further comprises applying a voltage between a source node and a drain node such that a pn-junction between the body region and the drift region of the at least one transistor cell is forward biased.

5. The method of claim 1 , wherein the superjunction transistor device has a voltage blocking capability, and wherein a magnitude of the bias voltage is less than 20% of the voltage blocking capability.

6. The method of claim 1 , wherein applying the bias voltage comprises providing the bias voltage by a bias voltage source and closing a first switch connected between the bias voltage source and one of the drift region and the compensation region.

7. The method of claim 1 , wherein the superjunction transistor device is a vertical transistor device integrated in a semiconductor body, and wherein the bias voltage is connected between the compensation region and the drift region via contacts arranged on top of a first surface of the semiconductor body.

8. The method of claim 1 , further comprising:
operating the superjunction transistor device in a reverse conducting state before operating the superjunction transistor device in the diode state,
wherein operating the superjunction transistor device in the reverse conducting state comprises:
applying a drive potential to a gate electrode of the at least one transistor cell such that there is a conducting channel in the body region of the at least one transistor cell; and
applying a voltage between the body region and the drift region and that has a same polarity as in the diode state.

9. The method of claim 1 , further comprising:
operating the superjunction transistor device in a blocking state after the diode state,
wherein operating the superjunction transistor device in the blocking state comprises:
applying a drive potential to a gate electrode of the at least one transistor cell such that a conducting channel in the body region of the at least one transistor cell is interrupted; and
applying a voltage between the body region and the drift region that has a polarity opposite a polarity of the voltage between the body region and the drift region in the diode state.

10. The method of claim 9 , wherein an inductive load is connected in parallel with the superjunction transistor device and an electronic switch is connected in series with the superjunction transistor device, and wherein changing an operating state of the superjunction transistor device from the diode state to the blocking state comprises changing a switching state of the electronic switch from an off-state to an on-state.

11. The method of claim 9 , further comprising:
operating the superjunction transistor device in one of a reverse conducting state and a forward conducting state after the blocking state,
wherein operating the superjunction transistor device in the reverse conducting state or the forward conducting comprises connecting the compensation region to a source node.

12. A transistor arrangement, comprising:
a transistor device comprising a bias region coupled to a bias node and at least one transistor cell comprising a source region, a body region, a compensation region, and a drift region; and
a first electronic switch connected between the bias region and the bias node,
wherein the transistor device and the first electronic switch are integrated in a common semiconductor body,
wherein the bias node is different from a source node and a gate node of the transistor arrangement,
wherein the bias node is configured such that a bias voltage between the bias node and the source node will reverse bias a pn-junction between the compensation region and the drift region when the transistor device is in a diode state.

13. The transistor arrangement of claim 12 , further comprising:
a second electronic switch integrated in the common semiconductor body,
wherein the second electronic switch is connected between the compensation region and the source region.

14. The transistor arrangement of claim 12 , wherein the bias region is the compensation region, and wherein the compensation region is spaced apart from the body region of the at least one transistor cell.

15. The transistor arrangement of claim 12 , wherein the bias region is spaced apart from the compensation region and the body region.

16. The transistor arrangement of claim 12 , wherein the compensation region is coupled to the bias node.

17. The transistor arrangement of claim 12 , wherein the bias region is connected to the bias node through a contact region that is more highly doped than the bias region and that provides an ohmic contact between the bias node and the bias region.

18. The transistor arrangement of claim 12 , wherein the first electronic switch is connected between a voltage source and the bias node.

19. The transistor arrangement of claim 12 , wherein the bias region is separated from the body region by a gate electrode and a gate dielectric of the at least one transistor cell and by a section of the drift region.

20. The transistor arrangement of claim 12 , wherein the bias region is separated from the body region by a trench filled with a dielectric.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Fachmann Christian
• Hirler Franz
• Kutschak Matteo-Alessandro
• Riegler Andreas

Classifications

• H10D84/839

  comprising VDMOS · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D84/143

  the built-in components being PN junction diodes · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title