Semiconductor device package comprising side walls connected with contact pads of a semiconductor die

Patent metadata

Field	Value
Publication number	US-11978693-B2
Application number	US-202117388248-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Jul 30, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

First claim

The invention claimed is:

1. A semiconductor device package, comprising:
a printed circuit board comprising a first central area, a second lateral area, and a third lateral area;
a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, the semiconductor die being disposed in the first central area of the printed circuit board;
a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board;
a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board;
wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad of the semiconductor die.

2. The semiconductor device package according to claim 1 , wherein one of the first metallic side wall and the second metallic side wall is electrically connected to the first contact pad of the semiconductor die, and the other one of the first metallic side wall the and the second metallic side wall is electrically connected to the second contact pad of the semiconductor die.

3. The semiconductor device package according to claim 2 , further comprising:
a first metallic via bar connected between the first contact pad of the semiconductor die and the first metallic side wall, and
a second metallic via bar connected between the second contact pad of the semiconductor die and the second metallic side wall.

4. The semiconductor device package according to claim 1 , further comprising:
a first upper main face of the semiconductor device package and a second lower main face of the semiconductor device package,
wherein at least one of the first metallic side wall and the second metallic side wall is exposed at the first upper main face and/or at the second lower main face of the semiconductor device package.

5. The semiconductor device package according to claim 2 , wherein the first metallic side wall and the second metallic side wall are exposed at the first upper main face and/or at the second lower main face of the semiconductor device package.

6. The semiconductor device package according to claim 1 , further comprising an isolation distance between the second contact pad and the first metallic side wall or the second metallic side wall electrically connected with the first contact pad, is in a range between 100 μm and 300 μm.

7. The semiconductor device package according to claim 1 , further comprising
a laminate layer disposed on the printed circuit board, wherein
the first metallic side wall, the second metallic side wall, the first metallic via bar, and the second metallic via bar are disposed within areas of the laminate layer.

8. A semiconductor device package, comprising:
a printed circuit board comprising a first central area;
a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, the semiconductor die being disposed in the first central area of the printed circuit board;
a first metallic via bar disposed on the first contact pad of the semiconductor die, the first metallic via bar comprising a thickness of at least 100 μm;
a second metallic via bar disposed on the second contact pad of the semiconductor die, the second metallic via bar comprising a thickness of at least 100 μm; and
at least one metallic side wall disposed in at least one area of the printed circuit board,
wherein the at least one metallic side wall is exposed at the first main face and/or at the second main face of the semiconductor device package.

9. The semiconductor device package according to claim 8 , wherein a thickness of each one of the first metallic via bar and the second metallic via bar is in a range from 100 μm to 300 μm.

10. The semiconductor device package according to claim 8 , further comprising:
the printed circuit board further comprising a second lateral area, and a third lateral area,
wherein a first metallic side wall of the at least one metallic side wall is disposed in the second lateral area of the printed circuit board,
wherein a second metallic side wall of the at least one metallic side wall is disposed in the third lateral area of the printed circuit board, and
wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first die pad or the second die pad of the semiconductor die.

11. The semiconductor device package according to claim 10 , wherein the first metallic via bar is connected between the first contact pad of the semiconductor die and the first metallic side wall, and the second metallic via bar is connected between the second contact pad of the semiconductor die and the second metallic side wall.

12. The semiconductor device package according to claim 8 , further comprising:
a laminate layer disposed on the printed circuit board,
wherein a first metallic side wall of the at least one metallic side wall, a second metallic side wall of the at least one metallic side wall, the first metallic via bar, and the second metallic via bar are disposed within areas of the laminate layer.

Assignees

• Infineon Technologies Ag

Inventors

• Palm Petteri
• Froehler Ulrich
• Otremba Ralf
• Riegler Andreas

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/07236

  Soldering or alloying · CPC title