Multi-die-package and method

Patent metadata

Field	Value
Publication number	US-12014973-B2
Application number	US-202117368169-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Nov 17, 2017
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

First claim

What is claimed is:

1. A method, comprising:
providing a processed first wafer having a front side, a back side and including a plurality of power semiconductor dies that have been implemented within the processed first wafer by processing its front side, each power semiconductor die having a first load terminal at the front side and a second load terminal at the back side;
providing an unprocessed second wafer made of an electrically insulating material and having a first side and a second side opposite thereof;
forming a plurality of recesses within the second wafer;
filling the plurality of recesses with a conductive material;
forming a stack by attaching, prior or subsequent to filling the plurality of recesses with the conductive material, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and
ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

2. The method of claim 1 , further comprising configuring the second wafer as a coupling layer, wherein one of the first side and the second side of the second wafer is being configured to be coupled to a lead frame structure.

3. The method of claim 2 , further comprising:
separating the stack into a plurality of stack units; and
arranging at least one of the stack units within a package body of a package, wherein arranging the at least one stack unit includes electrically connecting the conductive material with the lead frame structure.

4. The method of claim 1 , wherein each first load terminal is arranged in accordance with a layout structure, and wherein forming the plurality of recesses within the second wafer is carried out in dependence of the layout structure.

5. The method of claim 1 , wherein each first load terminal is surrounded by an edge termination region of the respective power semiconductor die, and wherein, while attaching the second wafer to the front side of the first wafer, ensuring that the edge termination region is covered only by the insulating material of the second wafer.

6. The method of claim 1 , wherein forming the plurality of recesses within the second wafer comprises, before or after filling the plurality of recesses with the conductive material, transforming the recesses into pass-through passages.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Riegler Andreas
• Fachmann Christian

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W70/461

  specially adapted for cooling · CPC title

• H10W70/427

  Bent parts · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title