Channel pattern design to improve carrier transfer efficiency
US-2025344528-A1 · Nov 6, 2025 · US
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Hsieh Te-Hsien patents
Hsieh Te-Hsien is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hsieh Te-Hsien |
| Total patents | 32 |
| First publication | Feb 5, 2015 |
| Latest publication | Nov 6, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Via landing on first and second barrier layers to reduce cleaning time of conductive structure
US-12456677-B2 · Oct 28, 2025 · US
Ion beam etching chamber with etching by-product redistributor
US-2025316457-A1 · Oct 9, 2025 · US
Ion beam etching chamber with etching by-product redistributor
US-12424419-B2 · Sep 23, 2025 · US
Ion beam etching chamber with etching by-product redistributor
US-12362154-B2 · Jul 15, 2025 · US
Semiconductor device and system for optical signal processing
US-2025224563-A1 · Jul 10, 2025 · US
Channel pattern design to improve carrier transfer efficiency
US-2025048753-A1 · Feb 6, 2025 · US
Channel pattern design to improve carrier transfer efficiency
US-12183764-B2 · Dec 31, 2024 · US
Isolation structures and methods of forming the same
US-2024332061-A1 · Oct 3, 2024 · US
Ion beam etching chamber with etching by-product redistributor
US-2023369024-A1 · Nov 16, 2023 · US
Recent patents
Latest publications not already listed above.
Via landing on first and second barrier layers to reduce cleaning time of conductive structure
US-2023361024-A1 · Nov 9, 2023 · US
Via landing on first and second barrier layers to reduce cleaning time of conductive structure
US-11776901-B2 · Oct 3, 2023 · US
3D RRAM cell structure for reducing forming and set voltages
US-11751406-B2 · Sep 5, 2023 · US
Channel pattern design to improve carrier transfer efficiency
US-2023253435-A1 · Aug 10, 2023 · US
High density memory devices with low cell leakage and methods for forming the same
US-11690232-B2 · Jun 27, 2023 · US
Via landing on first and second barrier layers to reduce cleaning time of conductive structure
US-2022293515-A1 · Sep 15, 2022 · US
Ion beam etching chamber with etching by-product redistributor
US-2022148856-A1 · May 12, 2022 · US
Ion beam etching chamber with etching by-product redistributor
US-11239060-B2 · Feb 1, 2022 · US
High density memory devices with low cell leakage and methods for forming the same
US-2021375993-A1 · Dec 2, 2021 · US
3d rram cell structure for reducing forming and set voltages
US-2021366987-A1 · Nov 25, 2021 · US
3D RRAM cell structure for reducing forming and set voltages
US-11088203-B2 · Aug 10, 2021 · US
3d rram cell structure for reducing forming and set voltages
US-2021036057-A1 · Feb 4, 2021 · US
Ion beam etching chamber
US-2019371574-A1 · Dec 5, 2019 · US
Pattern verifying method
US-9785046-B2 · Oct 10, 2017 · US
Method for optimizing an integrated circuit layout design
US-9747404-B2 · Aug 29, 2017 · US
Method for optimizing an integrated circuit layout design
US-2017024506-A1 · Jan 26, 2017 · US
Pattern verifying method
US-2016147140-A1 · May 26, 2016 · US
Method and apparatus for integrated circuit design
US-9262820-B2 · Feb 16, 2016 · US
Method and apparatus for integrated circuit design
US-2015332449-A1 · Nov 19, 2015 · US
Method of optical proximity correction
US-9047658-B2 · Jun 2, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 24 |
| United Microelectronics Corp | 9 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G03F1/36 | 8 |
| H10P72/7624 | 7 |
| H10P50/283 | 7 |
| H10P50/267 | 7 |
| H10P50/242 | 7 |