Channel pattern design to improve carrier transfer efficiency

Patent metadata

Field	Value
Publication number	US-2023253435-A1
Application number	US-202217735420-A
Country	US
Kind code	A1
Filing date	May 3, 2022
Priority date	Feb 8, 2022
Publication date	Aug 10, 2023
Grant date	—

Abstract

The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.

First claim

What is claimed is:

1 . An image sensor integrated chip, comprising:
a photodiode region disposed within a substrate comprising a first semiconductor material region; a second semiconductor material region disposed onto the substrate; a patterned doped layer arranged between the substrate and the second semiconductor material region; and wherein the second semiconductor material region comprises a sidewall connecting to a bottom surface of the second semiconductor material region, the sidewall extending through the patterned doped layer and the bottom surface being directly over the photodiode region.

2 . The image sensor integrated chip of claim 1 , wherein a sidewall of the patterned doped layer laterally contacts the sidewall of the second semiconductor material region along an interface that is directly over the photodiode region.

3 . The image sensor integrated chip of claim 1 , wherein the substrate comprises sidewalls and a horizontally extending surface defining a recess within an upper surface of the substrate, the second semiconductor material region being disposed within the recess.

4 . The image sensor integrated chip of claim 3 , further comprising:
a capping layer arranged on the second semiconductor material region and directly between the sidewalls of the substrate.

5 . The image sensor integrated chip of claim 1 , wherein the patterned doped layer comprises boron.

6 . The image sensor integrated chip of claim 1 , wherein the second semiconductor material region vertically extends to below a bottom of the patterned doped layer.

7 . The image sensor integrated chip of claim 1 , wherein the patterned doped layer is both laterally and vertically between the first semiconductor material region and the second semiconductor material region.

8 . The image sensor integrated chip of claim 1 , wherein the patterned doped layer is a same semiconductor material region as the first semiconductor material region.

9 . The image sensor integrated chip of claim 1 , wherein the photodiode region comprises:
a first doped region having a first doping type, wherein the first doped region is directly below the bottom surface of the second semiconductor material region; and a second doped region having a second doping type, wherein the second doped region comprises a vertically extending second doped region coupled to a horizontally extending second doped region that contacts a bottom of the first doped region.

10 . An image sensor integrated chip, comprising:
a photodiode region disposed within a silicon substrate; a patterned doped silicon layer disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly overlying the photodiode region; a germanium region disposed onto the patterned doped silicon layer, wherein the germanium region comprises a protrusion extending outward from a lower surface of the germanium region to directly between the sidewalls of the patterned doped silicon layer; a first interconnect coupled to a doped region, the doped region extending from the first interconnect to the photodiode region; and a second interconnect coupled to a first doped contact region, the first doped contact region disposed within the germanium region directly over both the photodiode region and the protrusion of the germanium region.

11 . The image sensor integrated chip of claim 10 , further comprising:
a dielectric structure disposed over the germanium region and the silicon substrate, wherein the dielectric structure laterally surrounds the first interconnect and the second interconnect.

12 . The image sensor integrated chip of claim 10 , further comprising:
a first dielectric structure disposed below the silicon substrate and surrounding the first interconnect; and a second dielectric structure disposed over the germanium region and surrounding the second interconnect.

13 . The image sensor integrated chip of claim 10 ,
wherein the patterned doped silicon layer comprises a plurality of sidewalls laterally separated from one another by the patterned doped silicon layer, the plurality of sidewalls defining a plurality of separate channel openings extending through the patterned doped silicon layer; and wherein the germanium region extends through the plurality of separate channel openings to contact the silicon substrate.

14 . The image sensor integrated chip of claim 13 , wherein the plurality of separate channel openings are disposed in an array and are separated from one another along a first direction and along a second direction that is perpendicular to the first direction, the first direction and the second direction being parallel to the lower surface of the germanium region.

15 . The image sensor integrated chip of claim 10 , wherein the protrusion laterally extends past opposing sides of the photodiode region.

16 . A method of forming an image sensor integrated chip, comprising:
forming a photodiode region within a substrate comprising a first semiconductor material region; forming a doped layer along an outer surface of the substrate and over the photodiode region; patterning the doped layer to form a patterned doped layer having one or more sidewalls that define one or more channel openings that extends through the patterned doped layer directly over the photodiode region; and forming a second semiconductor material region onto the patterned doped layer and within the one or more channel openings.

17 . The method of claim 16 , wherein forming the photodiode region comprises:
performing a first implantation process to form a first doped region having a first doping type; and performing a second implantation process to form a second doped region having a second doping type, the second doped region below the first doped region.

18 . The method of claim 17 , wherein the second doped region comprises a horizontally extending second doped region extending below a bottom of the second semiconductor material region and a vertically extending second doped region extending along a sidewall of the second semiconductor material region.

19 . The method of claim 16 , further comprising:
patterning the substrate to form a recess within an upper surface of the substrate; forming the second semiconductor material region within the recess; and performing a planarization process to remove excess of the second semiconductor material region from over the substrate.

20 . The method of claim 16 , further comprising:
performing an etching process to recess the second semiconductor material region below an upper surface of the substrate; forming a capping layer over the second semiconductor material region; and forming a doped contact region within the capping layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yung-Chang
• Lin Shih-Wei
• Hsieh Te-Hsien
• Lin Jung-I

Classifications

• H10F39/011 Primary

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/804

  Containers or encapsulations · CPC title

• H10F39/8033 Primary

  Photosensitive area · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title