High density memory devices with low cell leakage and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11690232-B2
Application number	US-202016885346-A
Country	US
Kind code	B2
Filing date	May 28, 2020
Priority date	May 28, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.

First claim

What is claimed is:

1. A memory device, comprising:
a first array of rail structures that extend along a first horizontal direction and are laterally spaced apart along a second horizontal direction, wherein each of the rail structures of the first array comprises a bottom electrode;
a second array of rail structures that laterally extend along the second horizontal direction and are laterally spaced apart along the first horizontal direction, wherein each of the rail structures of the second array comprises a top electrode; and
a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures, wherein the continuous dielectric memory layer spans a full length and a full width of the first array of rail structures and spans a full length and a full width of the second array of rail structures,
wherein the bottom electrode is directly connected to a respective metal interconnect structure formed above the bottom electrode.

2. The memory device of claim 1 , wherein the continuous dielectric memory layer comprises alumina (Al 2 O 3 ), hafnia (HfO 2 ), zirconia (ZrO 2 ), titanium dioxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ) and SZO (SrZrO 3 ).

3. The memory device of claim 2 , wherein the top electrode or the bottom electrode further comprises a selector material layer located between the continuous dielectric memory layer and a top surface of the bottom electrode or between the continuous dielectric memory layer and a bottom surface of the top electrode.

4. The memory device of claim 1 , wherein the continuous dielectric memory layer comprises a high-k dielectric memory material.

5. The memory device of claim 1 , wherein a least one of the first array of rail structures comprises a conductive material selected from TiN, W, TaN, Ti, Mo, Ru, Ni and mixtures thereof and at least one of the second array of rail structures comprises a conductive material selected from TiN, W, TaN, Ti, Mo, Ru, Ni and mixtures thereof.

6. The memory device of claim 1 , further comprising:
bit lines electrically connected to one of the bottom electrodes or the top electrodes; and
word lines electrically connected to the other of the bottom electrodes or the top electrodes.

7. At least two adjacent resistive random access memory cells:
wherein:
each of the at least two adjacent resistive random access memory cells comprises a first rail structure that extends along a first horizontal direction and is laterally spaced apart from an adjacent first rail structure along a second horizontal direction, wherein each of the first rail structures comprises a bottom electrode;
each of the at least two memory cells comprises a second rail structure that laterally extends along the second horizontal direction and is laterally spaced apart from an adjacent second rail structure along the first horizontal direction, wherein each of the second rail structures comprises a top electrode;
a continuous dielectric memory layer formed between the first rail structures and the second rail structures, wherein the continuous dielectric memory layer comprises a resistive switching material and spans a full length and width of the first rail structures and the second rail structures, and
at least one of the bottom electrode and the top electrode is electrically connected to a respective metal interconnect structure formed above the at least one of the bottom electrode and the top electrode.

8. The resistive random access memory device at least two adjacent resistive random access memory cells of claim 7 , wherein the resistive switching material comprises alumina (Al 2 O 3 ), hafnia (HfO 2 ), zirconia (ZrO 2 ), titanium dioxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ) and SZO (SrZrO 3 ).

9. The at least two adjacent resistive random access memory cells of claim 7 , wherein the at least two adjacent resistive random access memory cells
are formed over two levels of metal interconnect structures over a substrate.

10. A method of forming a memory device, comprising:
forming a first array of rail structures over a substrate that extend along a first horizontal direction;
forming a continuous dielectric memory layer located over the first array of rail structures;
forming a second array of rail structures over the continuous dielectric memory layer, wherein the second array of rail structures laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction,
wherein:
the continuous dielectric memory layer comprises a plate shape that spans a full length and width of the first array of rail structures and a second array of rail structures,
each of the rail structures in the first array of rails structures comprises a bottom electrode, and
each of the rail structures in the second array of rails structures comprises a top electrode; and

directly connecting at least one of the bottom electrode and the top electrode to a respective metal interconnect structure formed above the at least one of the bottom electrode and the top electrode.

11. A memory device, comprising:
bottom electrode rails that extend along a first horizontal direction and are laterally spaced apart along a second horizontal direction;
top electrode rails that laterally extend along the second horizontal direction and are laterally spaced apart along the first horizontal direction;
a continuous dielectric memory layer located between the bottom electrode rails and the top electrode rails, wherein the continuous dielectric memory layer spans a full length and a full width of the bottom electrode rails and spans a full length and a full width of the top electrode rails; and
bit line contact structures vertically extending through the continuous dielectric memory layer and contacting a top surface of a respective one of the bottom electrode rails.

12. The memory device of claim 11 , further comprising dielectric material rails laterally extending along the second horizontal direction and interlaced with the top electrode rails along the first horizontal direction.

13. The memory device of claim 12 , further comprising selector material rails laterally extending along the second horizontal direction and having a same area as a respective one of the top electrode rails and contacting a horizontal surface of the respective one of the top electrode rails.

14. The memory device of claim 13 , wherein each of the selector material rails overlies the respective one of the top electrode rails and has a respective top surface located within a same horizontal plane as top surfaces of the dielectric material rails.

15. The memory device of claim 14 , further comprising:
an interconnect-level dielectric layer overlying the selector material rails; and
metal via structures vertically extending through the interconnect-level dielectric layer and contacting a top surface of a respective one of the selector material rails.

16. The memory device of claim 13 , wherein each of the selector material rails underlies the respective one of the top electrode rails, and each of the top electrode rails has a respective top surface located within a same horizontal plane as top surfaces of the dielectric material rails.

17. The memory device of claim 12 , further comprising a dielectric material portion having a same material composition as, and having a same thickness as, the dielectric material rails, and having a top surface within a horizontal plane that contains top surfaces of the dielectric material rails,
wherein the bit line contact via structures vertic

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Te-Hsien
• Tseng Yuan-Tai

Classifications

• H10N70/841

  Electrodes · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title