Via landing on first and second barrier layers to reduce cleaning time of conductive structure

Patent metadata

Field	Value
Publication number	US-12456677-B2
Application number	US-202318353997-A
Country	US
Kind code	B2
Filing date	Jul 18, 2023
Priority date	Mar 10, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

First claim

What is claimed is:

1. An integrated chip, comprising:
a conductive structure arranged within a substrate or a first dielectric layer;
a first barrier layer arranged on outermost sidewalls and a bottom surface of the conductive structure;
a second barrier layer arranged on outer surfaces of the first barrier layer, wherein the second barrier layer separates the first barrier layer from the substrate or the first dielectric layer;
a second dielectric layer arranged over the substrate or the first dielectric layer; and
a via structure extending through the second dielectric layer, arranged directly over topmost surfaces of the first and second barrier layers, and electrically coupled to the conductive structure through the first and second barrier layers, wherein the via structure has a smaller width than the conductive structure as viewed in a cross-sectional view.

2. The integrated chip of claim 1 , wherein the via structure directly contacts the topmost surfaces of the first and second barrier layers.

3. The integrated chip of claim 1 , further comprising:
a third barrier structure arranged on outermost sidewalls and a bottom surface of the via structure, wherein the third barrier structure directly contacts the topmost surfaces of the first and second barrier layers.

4. The integrated chip of claim 1 , wherein the first barrier layer comprises a first conductive material, wherein the second barrier layer comprises a second conductive material, wherein the conductive structure comprises a third conductive material, and wherein the first conductive material and the second conductive material are more resistant to oxidation than the third conductive material.

5. The integrated chip of claim 1 , further comprising:
a third dielectric layer arranged over the via structure;
an additional conductive structure extending through the third dielectric layer and electrically coupled to the via structure;
a third barrier layer arranged on outermost sidewalls and a bottom surface of the additional conductive structure, wherein the third barrier layer comprises a same material as the first barrier layer; and
a fourth barrier layer arranged on outer surfaces of the third barrier layer, wherein the fourth barrier layer separates the third barrier layer from the third dielectric layer and the via structure.

6. The integrated chip of claim 1 , wherein the conductive structure comprises aluminum, and wherein the first barrier layer comprises titanium.

7. The integrated chip of claim 1 , further comprising:
a source region within the substrate and on a first side of the conductive structure; and
a drain region within the substrate and on a second side of the conductive structure, wherein the source and drain regions are spaced apart from the conductive structure by the first and second barrier layers.

8. The integrated chip of claim 1 , wherein a bottommost surface of the via structure directly overlies a top surface of the conductive structure.

9. The integrated chip of claim 1 , wherein a top surface of the conductive structure is completely covered by the second dielectric layer.

10. An integrated chip, comprising:
a conductive structure arranged within a substrate or a first dielectric layer;
a first barrier layer arranged on outermost sidewalls and a bottom surface of the conductive structure;
a second barrier layer arranged on outer surfaces of the first barrier layer, wherein the second barrier layer separates the first barrier layer from the substrate or the first dielectric layer;
an additional conductive structure arranged within the substrate or the first dielectric layer and laterally separated from the conductive structure;
a first additional barrier layer arranged on outermost sidewalls and a bottom surface of the additional conductive structure;
a second additional barrier layer arranged on outer surfaces of the first additional barrier layer;
a second dielectric layer arranged over the substrate or the first dielectric layer;
a via structure extending through the second dielectric layer, having a bottommost surface arranged directly over topmost surfaces of the first and second barrier layers, and electrically coupled to the conductive structure, wherein the via structure is arranged directly over a sidewall of the first barrier layer facing away from the additional conductive structure; and
an additional via structure extending through the second dielectric layer, having a bottommost surface arranged directly over topmost surfaces of the first and second additional barrier layers, and electrically coupled to the additional conductive structure, wherein the additional via structure is arranged directly over a sidewall of the first additional barrier layer facing towards the conductive structure.

11. The integrated chip of claim 10 , wherein the topmost surface of the first barrier layer has a first width, wherein the topmost surface of the second barrier layer has a second width, wherein the bottommost surface of the via structure has a third width, and wherein a sum of the first width and the second width is greater than or equal to the third width.

12. The integrated chip of claim 10 , wherein the conductive structure has an outermost sidewall comprising copper and the first barrier layer comprises titanium nitride contacting the outermost sidewall of the conductive structure.

13. The integrated chip of claim 10 , wherein the bottommost surface of the via structure directly overlies the substrate or the first dielectric layer.

14. The integrated chip of claim 10 , wherein the bottommost surface of the via structure directly contacts the first and second barrier layers.

15. The integrated chip of claim 10 , wherein the topmost surface of the first barrier layer has a first width, wherein the topmost surface of the second barrier layer has a second width, wherein the bottommost surface of the via structure has a third width, and wherein a sum of the first width and the second width is less than the third width.

16. The integrated chip of claim 15 , wherein a top surface of the conductive structure is completely covered by the second dielectric layer, and wherein the bottommost surface of the via structure directly overlies the substrate or the first dielectric layer.

17. The integrated chip of claim 10 , wherein the via structure is laterally off-centered from the conductive structure and centered upon the topmost surfaces of the first and second barrier layers.

18. An integrated chip, comprising:
a conductive structure arranged within a substrate or a first dielectric;
source/drain regions disposed within the substrate along opposing sides of the conductive structure;
a first barrier layer arranged along one or more outer surfaces of the conductive structure;
a second barrier layer arranged along one or more outer surfaces of the first barrier layer, wherein the first barrier layer physically separates the second barrier layer from the conductive structure;
a second dielectric arranged over the substrate or the first dielectric; and
a via structure extending through the second dielectric to the first and second barrier layers, wherein the via structure laterally extends past an outermost sidewall of the second barrier layer.

19. The integrated chip of claim 18 , wherein a bottom of the via structure extends to over the substrate or the first dielectric.

20. The integrated chip of claim 18 , wherein the first barrier layer is titanium nitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Te-Hsien
• Chang Yu-Hsing
• Chen Yi-Min

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title