Method for optimizing an integrated circuit layout design

Patent metadata

Field	Value
Publication number	US-2017024506-A1
Application number	US-201514807869-A
Country	US
Kind code	A1
Filing date	Jul 23, 2015
Priority date	Jul 23, 2015
Publication date	Jan 26, 2017
Grant date	—

Abstract

A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

First claim

What is claimed is:

1 . A method for optimizing an integrated circuit layout design, comprising:
obtaining a first integrated circuit layout design comprising a metal line feature having several metal lines and a second integrated circuit layout design comprising a hole feature having several holes by a computer system; selecting a line-end hole feature of the hole feature by piecing the metal line feature with the hole feature by the computer system; and classifying the line-end hole feature into a single hole feature and a redundant hole feature by spacings between the adjacent holes by the computer system.

2 . The method for optimizing an integrated circuit layout design according to claim 1 , wherein the step of selecting the line-end hole feature of the hole feature comprises:
piecing the metal line feature with the hole feature; and recognizing the line-end hole feature by selecting the holes in ends of the metal lines, where line-widths become thinner.

3 . The method for optimizing an integrated circuit layout design according to claim 1 , wherein the step of classifying the line-end hole feature into the single hole feature and the redundant hole feature comprises:
as the spacings between the adjacent holes exceed a minimum dense hole space tolerance, the adjacent holes classified into the single hole feature, and as the spacings between the adjacent holes fall in the minimum dense hole space tolerance, the adjacent holes classified into the redundant hole feature.

4 . The method for optimizing an integrated circuit layout design according to claim 3 , wherein the minimum dense hole space tolerance comprises a predetermined minimum dense hole space +/−10%.

5 . The method for optimizing an integrated circuit layout design according to claim 4 , wherein the minimum dense hole space tolerance comprises a predetermined minimum dense hole space.

6 . The method for optimizing an integrated circuit layout design according to claim 1 , further comprising:
performing a repairing method only on the single hole feature by the computer system after classifying the line-end hole feature.

7 . The method for optimizing an integrated circuit layout design according to claim 6 , wherein the repairing method comprises identifying defects of the single hole feature and then repairing the defects.

8 . The method for optimizing an integrated circuit layout design according to claim 6 , wherein the repairing method comprises an optical proximity correction (OPC) treatment process.

9 . The method for optimizing an integrated circuit layout design according to claim 6 , wherein the repairing method comprises an enclosure check process.

10 . The method for optimizing an integrated circuit layout design according to claim 1 , further comprising:
conducting an on-rule step to confirm the line-end hole feature is applicative by the computer system.

11 . The method for optimizing an integrated circuit layout design according to claim 10 , wherein the on-rule step is conducted after selecting the line-end hole feature.

12 . The method for optimizing an integrated circuit layout design according to claim 10 , wherein the on-rule step comprises confirming the holes of the line-end hole feature are in the metal lines.

13 . The method for optimizing an integrated circuit layout design according to claim 10 , wherein the on-rule step comprises confirming minimum widths and minimum spacings of the metal lines are applicative.

14 . The method for optimizing an integrated circuit layout design according to claim 1 , wherein the hole feature comprises the line-end hole feature and a normal hole feature.

15 . The method for optimizing an integrated circuit layout design according to claim 14 , wherein the hole feature comprises a static random access memory (SRAM) hole feature.

16 . The method for optimizing an integrated circuit layout design according to claim 1 , wherein the metal line feature and the hole feature are printed in adjacent layers of a wafer.

Assignees

• United Microelectronics Corp

Inventors

• Kuo Shih-Ming
• Chen Ming-Jui
• Hsieh Te-Hsien
• Hsieh Ping-I
• Lee Jing-Yi
• Chen yan-chun

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic