Channel pattern design to improve carrier transfer efficiency

Patent metadata

Field	Value
Publication number	US-2025344528-A1
Application number	US-202519269108-A
Country	US
Kind code	A1
Filing date	Jul 15, 2025
Priority date	Feb 8, 2022
Publication date	Nov 6, 2025
Grant date	—

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a first doped region disposed within a substrate. A first conductive interconnect is arranged within a first dielectric structure disposed on a first side of the substrate. The first conductive interconnect is electrically coupled to the first doped region. A patterned doped layer is arranged along a surface of the substrate. The patterned doped layer has sidewalls that form one or more openings. A semiconductor material is arranged over the patterned doped layer and within the one or more openings. A second doped region is disposed along an upper surface of the semiconductor material. The one or more openings are vertically between the first doped region and the second doped region.

First claim

1 - 20 . (canceled)

21 . An integrated chip, comprising:
a first doped region disposed within a substrate; a first conductive interconnect arranged within a first dielectric structure disposed on a first side of the substrate, the first conductive interconnect being electrically coupled to the first doped region; a patterned doped layer arranged along a surface of the substrate, the patterned doped layer having sidewalls that form one or more openings; a semiconductor material arranged over the patterned doped layer and within the one or more openings; and a second doped region disposed along an upper surface of the semiconductor material, the one or more openings being vertically between the first doped region and the second doped region.

22 . The integrated chip of claim 21 , wherein the semiconductor material extends to a non-zero distance below a bottom of the patterned doped layer.

23 . The integrated chip of claim 21 , wherein the first doped region and the second doped region laterally extend past the sidewalls of the patterned doped layer.

24 . The integrated chip of claim 21 , further comprising:
a second conductive interconnect arranged within a second dielectric structure disposed on a second side of the substrate, the second conductive interconnect being electrically coupled to the second doped region; and a second substrate stacked onto the substrate, wherein the second dielectric structure is between the substrate and the second substrate.

25 . The integrated chip of claim 21 , wherein the substrate comprises silicon and the patterned doped layer comprises boron doped silicon.

26 . The integrated chip of claim 21 , further comprising:
a cap layer arranged over the semiconductor material, the second doped region being arranged within the cap layer.

27 . The integrated chip of claim 21 , further comprising:
a second conductive interconnect arranged within the first dielectric structure, the second conductive interconnect being electrically coupled to the second doped region; and a second substrate stacked onto the substrate, wherein the first dielectric structure is between the substrate and the second substrate.

28 . The integrated chip of claim 21 , wherein the semiconductor material has a central region and a peripheral region laterally surrounding the central region along a first direction and along a second direction that is perpendicular to the first direction in a top-view, the central region having a larger thickness than the peripheral region measured along a third direction that is perpendicular to both the first direction and the second direction.

29 . An integrated chip, comprising:
a first doped region within a substrate, the substrate having one or more interior surfaces forming a recess within an upper surface of the substrate; a single photon avalanche diode (SPAD) region within the substrate and vertically between a part of the first doped region and the recess; a doped layer arranged along the one or more interior surfaces of the substrate, wherein the substrate is vertically and laterally between the first doped region from the doped layer; a semiconductor material arranged on the doped layer, wherein the semiconductor material punctures the doped layer to contact the substrate above the SPAD region; and wherein the doped layer continuously extends around the semiconductor material in a first closed loop as viewed in a sectional top-view and the first doped region continuously extends around the doped layer in a second closed loop as viewed in the sectional top-view.

30 . The integrated chip of claim 29 , wherein the semiconductor material extends through one or more openings extending through the doped layer to contact the substrate.

31 . The integrated chip of claim 30 , wherein the one or more openings are arranged within a one dimensional array in a second sectional top-view.

32 . The integrated chip of claim 30 , wherein the one or more openings are arranged within a two-dimensional array in a second sectional top-view.

33 . The integrated chip of claim 30 , wherein the semiconductor material laterally extends past the one or more openings in a first direction and in a second direction that is perpendicular to the first direction.

34 . The integrated chip of claim 29 , wherein the first doped region laterally and vertically extends past opposing sides of the SPAD region.

35 . A method, comprising:
implanting a first dopant into a substrate to form a doped region within the substrate; forming a doped semiconductor layer along one or more surfaces of the substrate; forming a dielectric masking layer on the doped semiconductor layer; etching the doped semiconductor layer according to the dielectric masking layer to expose an upper surface of the substrate; removing the dielectric masking layer; depositing a semiconductor material onto the doped semiconductor layer and the upper surface of the substrate; and implanting a second dopant to form a second doped region along an upper surface of the semiconductor material.

36 . The method of claim 35 , wherein the dielectric masking layer comprises silicon dioxide.

37 . The method of claim 35 , wherein the doped semiconductor layer is etched using a wet etchant.

38 . The method of claim 35 , further comprising:
performing a planarization process to remove part of the semiconductor material.

39 . The method of claim 35 , wherein the first dopant comprises an n-type dopant and the second dopant comprises a p-type dopant.

40 . The method of claim 35 , further comprising:
depositing a silicon layer onto tops of the doped semiconductor layer and the semiconductor material and onto a sidewall of the substrate, wherein the second dopant is implanted into the silicon layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yung-Chang
• Lin Shih-Wei
• Hsieh Te-Hsien
• Lin Jung-I

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/011 Primary

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• H10F39/804

  Containers or encapsulations · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/014

  of CMOS image sensors · CPC title