Via landing on first and second barrier layers to reduce cleaning time of conductive structure

Patent metadata

Field	Value
Publication number	US-11776901-B2
Application number	US-202117197381-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Mar 10, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

First claim

What is claimed is:

1. A method comprising:
forming a first opening within a substrate or a first dielectric layer;
forming a first barrier layer within the first opening;
forming a second barrier layer over the first barrier layer and within the first opening;
forming a conductive structure over the second barrier layer to fill the first opening;
forming a second dielectric layer over the conductive structure;
forming a second opening within the second dielectric layer, wherein the second opening exposes topmost surfaces of the first and second barrier layers; and
forming an interconnect structure within the second opening and over the topmost surfaces of the first and second barrier layers, wherein a bottom of the interconnect structure laterally straddles the topmost surfaces of the first barrier layer and the second barrier layer.

2. The method of claim 1 , wherein the second opening exposes the topmost surfaces of the first barrier layer and the second barrier layer and an upper surface of the first dielectric layer.

3. The method of claim 1 , wherein the first barrier layer comprises a first conductive material, wherein the second barrier layer comprises a second conductive material, wherein the conductive structure comprises a third conductive material, and wherein the first conductive material and the second conductive material are more resistant to oxidation than the third conductive material.

4. The method of claim 1 , wherein the second opening also exposes a top surface of the conductive structure.

5. The method of claim 1 , wherein the interconnect structure comprises an additional conductive material surrounded by an additional barrier layer, the additional conductive material having a bottommost surface that laterally extends from directly over the first barrier layer to directly over the second barrier layer.

6. A method comprising:
forming a conductive structure over a substrate, the conductive structure comprising a conductive material laterally surrounded by a lower barrier layer and an upper barrier layer over the lower barrier layer;
forming a dielectric layer over the conductive structure;
etching the dielectric layer to form an opening that exposes upper surfaces of the lower barrier layer, the upper barrier layer, and the conductive material;
forming a via structure within the opening and on the upper surfaces of the lower barrier layer, the upper barrier layer, and the conductive material;
forming a first upper dielectric layer over the dielectric layer and the via structure;
forming an additional conductive structure extending through the first upper dielectric layer to contact the via structure, the additional conductive structure comprising an additional conductive material laterally surrounded by an additional lower barrier layer and an additional upper barrier layer over the lower barrier layer; and
forming an additional via structure within a second upper dielectric formed over the first upper dielectric layer, the additional via structure contacting upper surfaces of the additional lower barrier layer and the additional upper barrier layer.

7. The method of claim 6 , wherein the via structure physically contacts the upper surfaces of the lower barrier layer, the upper barrier layer, and the conductive material.

8. The method of claim 6 , further comprising:
forming a via structure barrier layer within the opening; and
forming a conductive via material on the via structure barrier layer and within the opening.

9. The method of claim 6 , wherein the conductive material comprises aluminum and the upper barrier layer comprises titanium.

10. The method of claim 6 , further comprising:
forming the conductive material within a lower dielectric layer formed over the substrate, wherein the opening further exposes an upper surface of the lower dielectric layer.

11. The method of claim 6 , further comprising:
exposing the upper surfaces of the lower barrier layer, the upper barrier layer, and the conductive material to an environment that causes a metal-oxide residue to form along the upper surfaces of the lower barrier layer, the upper barrier layer, and the conductive material.

12. The method of claim 11 , further comprising:
performing a plasma cleaning process to remove the metal-oxide residue from the upper surfaces of the lower barrier layer and the upper barrier layer.

13. The method of claim 6 , wherein the additional upper barrier layer comprises a same material as the upper barrier layer.

14. The method of claim 6 , wherein a bottom surface of the via structure laterally straddles the upper surfaces of the lower barrier layer and the upper barrier layer.

15. A method comprising:
forming a first opening within a first dielectric layer formed over a substrate;
forming a lower barrier layer within the first opening;
forming an upper barrier layer over the lower barrier layer and within the first opening;
forming a conductive material over the upper barrier layer and within the first opening, wherein the conductive material has a lower resistance to oxidation than the upper barrier layer;
forming a second dielectric layer over the lower barrier layer, the upper barrier layer, and the conductive material;
forming a second opening extending through the second dielectric layer, the second opening exposing surfaces of the lower barrier layer, the upper barrier layer, and the first dielectric layer; and
forming a via structure within the second opening and on the surfaces of the lower barrier layer and the upper barrier layer.

16. The method of claim 15 , wherein the conductive material is a different material than the upper barrier layer.

17. The method of claim 15 , wherein the lower barrier layer comprises tantalum and the upper barrier layer comprises titanium nitride.

18. The method of claim 15 , further comprising:
forming a third opening within the first dielectric layer;
forming the lower barrier layer, the upper barrier layer, and the conductive material within the third opening;
forming a fourth opening extending through the second dielectric layer, the fourth opening exposing additional surfaces of the lower barrier layer and the upper barrier layer; and
forming an additional via structure within the fourth opening and contacting the additional surfaces of the lower barrier layer and the upper barrier layer.

19. The method of claim 15 , wherein a bottom surface of the via structure is completely laterally outside of the conductive material.

20. The method of claim 15 , wherein a bottom surface of the via structure laterally straddles an uppermost surface of the lower barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Te-Hsien
• Chang Yu-Hsing
• Chen Yi-Min

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title