3D RRAM cell structure for reducing forming and set voltages

Patent metadata

Field	Value
Publication number	US-11088203-B2
Application number	US-201916575663-A
Country	US
Kind code	B2
Filing date	Sep 19, 2019
Priority date	Jul 29, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
a substrate having a surface;
a metal interconnect structure formed over the surface;
a resistance switching random access memory (RRAM) cell formed within the metal interconnect structure, the RRAM cell comprising a bottom electrode layer, a top electrode layer, and a switching layer between the bottom electrode layer and the top electrode layer; and
an etch stop or interfacial layer underneath the bottom electrode layer and above the surface;
wherein a top of the top electrode layer and a top of the bottom electrode layer have equal height over the substrate.

2. The IC device of claim 1 , wherein:
the RRAM cell has edges that comprise the bottom electrode layer, the switching layer, and the top electrode layer; and
the edges all lie in a plane.

3. The IC device of claim 2 , wherein the plane is parallel to the surface.

4. The IC device of claim 1 , wherein the bottom electrode layer and the switching layer terminate at edges that form closed loops aligned in a plane.

5. The IC device of claim 1 , wherein the bottom electrode layer encompasses the switching layer.

6. The IC device of claim 5 , wherein the switching layer encompasses the top electrode layer.

7. The IC device of claim 1 , wherein the bottom electrode layer is surrounded by low κ dielectric layer.

8. The IC device of claim 1 , wherein the bottom electrode layer is surrounded by an extremely low κ dielectric layer.

9. The IC device of claim 1 , wherein:
the RRAM cell has a width and a height; and
the height is at least half the width.

10. An integrated circuit (IC) device, comprising:
a substrate having a surface;
a metal interconnect structure formed over the surface;
a resistance switching random access memory (RRAM) cell formed within the metal interconnect structure, the RRAM cell comprising a bottom electrode layer, a top electrode layer, and a switching layer between the bottom electrode layer and the top electrode layer; and
an etch stop or interfacial layer underneath the bottom electrode layer and above the surface;
wherein the RRAM cell has edges that comprise the bottom electrode layer, the switching layer, and the top electrode layer; and
the RRAM cell is curved, whereby the edges all lie in a plane.

11. The IC device of claim 10 , wherein the plane is parallel to the surface.

12. The IC device of claim 10 , wherein an edge of the bottom electrode layer forms a closed loop in the plane.

13. The IC device of claim 10 , wherein the bottom electrode layer encompasses the switching layer and the top electrode layer.

14. The IC device of claim 10 , wherein the bottom electrode layer is disposed in a matrix of low κ dielectric.

15. The IC device of claim 10 , wherein:
the RRAM cell has an area that includes a bottom area and a side area; and
the side area is greater than the bottom area.

16. A method of manufacturing an integrated circuit (IC) device, comprising:
forming a metal interconnect layer over a semiconductor substrate;
forming a dielectric layer over the metal interconnect layer, wherein the dielectric layer is a low-κ dielectric layer;
forming an opening in the dielectric layer;
forming a resistance switching random access memory (RRAM) cell stack over the opening;
planarizing the RRAM cell stack to form an RRAM cell within the opening;
prior to forming the low-κ dielectric layer, forming an etch stop layer over the metal interconnect layer;
forming a via opening in the etch stop layer; and
filling the via opening with metal to form a bottom electrode via for the RRAM cell.

17. The method of claim 16 , wherein:
the opening has a width and a height; and
the height is at least half the width.

18. The method of claim 16 , wherein:
forming the RRAM cell stack comprises successively forming a bottom electrode layer, a switching layer, and a top electrode layer;
forming the bottom electrode layer and the switching layer leaves the opening partially filled; and
forming the top electrode layer fills the opening.

19. The method of claim 16 , wherein the low κ dielectric layer is an extremely low κ dielectric layer.

20. The method of claim 16 , wherein:
the bottom electrode via passes through the etch stop layer and an interfacial layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Te-Hsien
• Chen Tzu-Yu
• Tu Kuo-Chi
• Tseng Yuan-Tai

Classifications

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L27/2436 Primary

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic