Voltage generator to compensate for process corner and temperature variations
US-9959915-B2 · May 1, 2018 · US
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Mui Man patents
Mui Man is listed as an inventor on 46 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mui Man |
| Total patents | 46 |
| First publication | Jan 6, 2015 |
| Latest publication | May 1, 2018 |
Notable patents
Publications ranked by popularity score, then publication date.
Techniques for programming of select gates in NAND memory
US-9947407-B2 · Apr 17, 2018 · US
Programming techniques for non-volatile memories with charge trapping layers
US-9947395-B2 · Apr 17, 2018 · US
Techniques For Programming Of Select Gates In NAND Memory
US-2017256317-A1 · Sep 7, 2017 · US
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
US-2017221556-A1 · Aug 3, 2017 · US
Voltage generator to compensate for process corner and temperature variations
US-2017169867-A1 · Jun 15, 2017 · US
Techniques for programming of select gates in NAND memory
US-9659656-B2 · May 23, 2017 · US
Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices
US-9633742-B2 · Apr 25, 2017 · US
Programming techniques for non-volatile memories with charge trapping layers
US-9627046-B2 · Apr 18, 2017 · US
Utilizing NAND strings in dummy blocks for faster bit line precharge
US-9595338-B2 · Mar 14, 2017 · US
Recent patents
Latest publications not already listed above.
Multi tier three-dimensional memory devices including vertically shared bit lines
US-9502471-B1 · Nov 22, 2016 · US
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
US-2016260476-A1 · Sep 8, 2016 · US
Techniques for programming of select gates in nand memory
US-2016189778-A1 · Jun 30, 2016 · US
Word line kick during sensing: trimming and adjacent word lines
US-9318210-B1 · Apr 19, 2016 · US
Zoned erase verify in three dimensional nonvolatile memory
US-9312026-B2 · Apr 12, 2016 · US
Techniques for programming of select gates in NAND memory
US-9305648-B2 · Apr 5, 2016 · US
Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge
US-2016086671-A1 · Mar 24, 2016 · US
Techniques for Programming of Select Gates in NAND Memory
US-2016055911-A1 · Feb 25, 2016 · US
Zoned Erase Verify in Three Dimensional Nonvolatile Memory
US-2016055918-A1 · Feb 25, 2016 · US
Back gate operation with elevated threshold voltage
US-9240238-B2 · Jan 19, 2016 · US
Pseudo block operation mode in 3D NAND
US-9240241-B2 · Jan 19, 2016 · US
Segmentation of Blocks for Faster Bit Line Settling/Recovery in Non-Volatile Memory Devices
US-2016012903-A1 · Jan 14, 2016 · US
Voltage kick to non-selected word line during programming
US-9236128-B1 · Jan 12, 2016 · US
Optimized configurable NAND parameters
US-9229856-B2 · Jan 5, 2016 · US
Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping
US-9218874-B1 · Dec 22, 2015 · US
Selection of data for redundancy calculation by likely error rate
US-9177673-B2 · Nov 3, 2015 · US
Bad block reconfiguration in nonvolatile memory
US-9142324-B2 · Sep 22, 2015 · US
System to reduce stress on word line select transistor during erase operation
US-9142305-B2 · Sep 22, 2015 · US
Selection of data for redundancy calculation by likely error rate
US-9136022-B2 · Sep 15, 2015 · US
Fast-reading NAND flash memory
US-9111627-B2 · Aug 18, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sandisk Technologies Inc | 41 |
| Sandisk Technologies Llc | 11 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/0483 | 39 |
| G11C16/10 | 29 |
| G11C16/26 | 20 |
| G11C11/5628 | 18 |
| G11C16/3427 | 17 |