Techniques for programming of select gates in nand memory

Patent metadata

Field	Value
Publication number	US-2016189778-A1
Application number	US-201615062987-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Aug 20, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

First claim

What is claimed is:

1 . A memory structure, comprising:
a plurality of serially-connected drain select transistors; a plurality of memory transistors coupled to the plurality of serially-connected drain select transistors; and one or more source select transistors coupled to the plurality of memory transistors, wherein the plurality of serially-connected drain select transistors comprises a first drain select transistor coupled to a bit line and a second drain select transistor coupled to the bit line via the first drain select transistor, and wherein a first gate terminal of the first drain select transistor is controllable separately from a second gate terminal of the second drain select transistor.

2 . The memory structure of claim 1 , wherein a threshold voltage of the second drain select transistor is programmable.

3 . The memory structure of claim 2 , wherein the threshold voltage of the second drain select transistor is programmable independently from a threshold voltage of the first drain select transistor.

4 . The memory structure of claim 3 , wherein during programming of the threshold voltage of the second drain select transistor, a conducting voltage level is applied to the first gate terminal and a programming pulse is applied to the second gate terminal.

5 . The memory structure of claim 2 , wherein the threshold voltage of the second drain select transistor is configured to have a positive value.

6 . The memory structure of claim 5 , wherein during programming of the plurality of memory transistors, the second gate terminal is biased at a voltage level below the threshold voltage of the second drain select transistor, thereby ensuring that the second drain select transistor is in a non-conducting state.

7 . The memory structure of claim 2 , wherein the plurality of serially-connected drain select transistors further comprises a third drain select transistor, coupled between the first drain select transistor and the second drain select transistor, and wherein a threshold voltage of the third drain select transistor is programmable jointly with the threshold voltage of the second drain select transistor.

8 . The memory structure of claim 1 , wherein the first drain select transistor is directly coupled to the bit line without an intervening transistor.

9 . The memory structure of claim 1 , wherein the one or more source select transistors comprise a first source select transistor coupled to a source line and a second source select transistor coupled to the source line via the first source select transistor, and wherein a third gate terminal of the first source select transistor is controllable separately from a fourth gate terminal of the second source select transistor.

10 . A memory array, comprising:
a plurality of source lines; a plurality of bit lines; and a plurality of memory structures, wherein at least one of the plurality of memory structures comprises:
a plurality of serially-connected drain select transistors;
a plurality of memory transistors coupled to the plurality of serially-connected drain select transistors; and
one or more source select transistors coupled to the plurality of memory transistors,
wherein the plurality of serially-connected drain select transistors comprises a first drain select transistor coupled to a first bit line of the plurality of bit lines and a second drain select transistor coupled to the first bit line via the first drain select transistor, and
wherein a first gate terminal of the first drain select transistor is controllable separately from a second gate terminal of the second drain select transistor.

11 . The memory array of claim 10 , wherein a threshold voltage of the second drain select transistor is programmable.

12 . The memory array of claim 11 , wherein the threshold voltage of the second drain select transistor is programmable independently from a threshold voltage of the first drain select transistor.

13 . The memory array of claim 12 , wherein during programming of the threshold voltage of the second drain select transistor, a conducting voltage level is applied to the first gate terminal and a programming pulse is applied to the second gate terminal.

14 . The memory array of claim 11 , wherein the threshold voltage of the second drain select transistor is configured to have a positive value.

15 . The memory array of claim 14 , wherein during programming of the plurality of memory transistors, the second gate terminal is biased at a voltage level below the threshold voltage of the second drain select transistor, thereby ensuring that the second drain select transistor is in a non-conducting state.

16 . The memory array of claim 10 , wherein the one or more source select transistors comprise a first source select transistor coupled to a first source line of the plurality of source lines and a second source select transistor coupled to the first source line via the first source select transistor, and wherein a third gate terminal of the first source select transistor is controllable separately from a fourth gate terminal of the second source select transistor.

17 . A memory structure, comprising:
a plurality of serially-connected source select transistors; a plurality of memory transistors coupled to the plurality of serially-connected source select transistors; and one or more drain select transistors coupled to the plurality of memory transistors, wherein the plurality of serially-connected source select transistors comprises a first source select transistor coupled to a source line and a second source select transistor coupled to the source line via the first source select transistor, and wherein a first gate terminal of the first source select transistor is controllable separately from a second gate terminal of the second source select transistor.

18 . The memory structure of claim 17 , wherein a threshold voltage of the second source select transistor is programmable independently from a threshold voltage of the first source select transistor.

19 . The memory structure of claim 17 , wherein during programming of the plurality of memory transistors, the second gate terminal is biased at a voltage level below a threshold voltage of the second source select transistor, thereby ensuring that the second source select transistor is in a non-conducting state.

20 . The memory structure of claim 17 , wherein the one or more drain select transistors comprise a first drain select transistor coupled to a bit line and a second drain select transistor coupled to the bit line via the first drain select transistor.

21 . A three-dimensional (3D) memory structure, comprising:
a plurality of serially-connected drain select transistors; a plurality of memory transistors coupled to the plurality of serially-connected drain select transistors; and one or more source select transistors coupled to the plurality of memory transistors, wherein the plurality of serially-connected drain select transistors comprises a first drain select transistor coupled to a bit line and a second drain select transistor coupled to the bit line via the first drain select transistor, and wherein each transistor of the plurality of serially-connected drain select transistors, the plurality of memory transistors, and the one or more source select transistors is disposed in a respective device layer of a plurality of device layers of the 3D memory structure, the plurality of device layers being disposed vertica

Assignees

• Sandisk Technologies Inc

Inventors

• Nguyen Hao
• Mui Man
• Nguyen Khanh
• Lee Seungpil
• Ishigaki Toru
• Dong Yingda

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title