Programming techniques for non-volatile memories with charge trapping layers

Patent metadata

Field	Value
Publication number	US-9627046-B2
Application number	US-201514635918-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Mar 2, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

First claim

It is claimed:

1. A method, comprising:
in a non-volatile memory circuit having an array of memory cells each having a dielectric charge storage medium, a plurality of which are formed along a first word line, performing a programming operation to program a plurality of memory cells along the first word line from an initial state to one of a plurality of programmed states, the programmed states including first and second programmed states, where at least one of the memory cells along the first word line are to be programmed to each of the first and second programmed states, the programming operation including:
performing a first programming sub-operation, including:
program inhibiting all memory cells not to be programmed to the first programmed state;
program enabling all memory cells to be programmed to the first programmed state; and
applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the first programmed state, wherein programmed enable memory cells that verify at the first programmed state are subsequently inhibited for subsequent programming pulses; and

subsequently performing a second programming sub-operation, including
program inhibiting all memory cells not to be programmed to the second programmed state;
program enabling all memory cells to be programmed to the second programmed state; and
applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the second programmed state, wherein programmed enable memory cells that verify at the second programmed state are subsequently inhibited for subsequent programming pulses.

2. The method of claim 1 , wherein the initial state is an erased state.

3. The method of claim 1 , wherein the first programmed state corresponds to a higher threshold voltage than the second programmed state.

4. The method of claim 1 , wherein the second programmed state corresponds to a higher threshold voltage than the first programmed state.

5. The method of claim 1 , wherein the series of programming pulses for both of the first and the second programming operations is a staircase of increasing amplitude.

6. The method of claim 5 , wherein the staircase corresponding to the one of the first and the second programmed state having the higher threshold voltage begins at a high voltage than the staircase corresponding to the other of the first and the second programmed state.

7. The method of claim 5 , wherein for the programming sub-operation corresponding to the one of the first and the second programmed state having the higher threshold voltage, a number of initial programming pulses are performed before alternating verify operations.

8. The method of claim 1 , wherein the array is formed according to a NAND type of architecture, each of the plurality of memory cells formed along the first word line being on a different NAND string of the array.

9. The method of claim 8 , wherein each of the NAND strings on which the plurality of memory cells formed along the first word line are formed is connected to an associated bit line, and wherein the programming enabling of a memory cell includes setting the bit line associated thereto to ground.

10. The method of claim 8 , wherein each of the NAND strings on which the plurality of memory cells formed along the first word line are formed is connected to an associated bit line, and wherein the programming inhibiting of a memory cell includes setting the bit line associated thereto to a voltage to allow the corresponding NAND string to float.

11. The method of claim 8 , further comprising:
prior to applying the programming pulses, setting others of the word lines of the NAND strings of the array to a non-selected word line programming pass voltage.

12. The method of claim 11 , further comprising:
raising the level of the non-selected word line programming pass voltage while applying one or more of the programming pulses.

13. The method of claim 8 , wherein each of the NAND strings on which the plurality of memory cells formed along the first word line are formed is connected to an associated bit line, and wherein a verify operation includes pre-charging the bit lines corresponding to the memory cells to be programmed in the preceding programming pulse.

14. The method of claim 1 , wherein the memory circuit is a monolithic two-dimensional semiconductor memory device in which the memory cells are arranged in single physical level above a silicon substrate.

15. The method of claim 1 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and word lines, including the first word line, run in a horizontal direction relative to the substrate.

16. A non-volatile memory circuit, comprising:
an array of memory cells each having a dielectric charge storage medium, a plurality of which are formed along a first word line; and
programming and sensing circuitry connectable to the array whereby, when performing a programming operation to program a plurality of memory cells along the first word line from an initial state to one of a plurality of programmed states, the programmed states including first and second programmed states, where at least one of the memory cells along the first word line are to be programmed to each of the first and second programmed states, including:
performing a first programming sub-operation, including:
program inhibiting all memory cells not to be programmed to the first programmed state;
program enabling all memory cells to be programmed to the first programmed state; and
applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the first programmed state, wherein programmed enable memory cells that verify at the first programmed state are subsequently inhibited for subsequent programming pulses; and
subsequently performing a second programming sub-operation, including:
program inhibiting all memory cells not to be programmed to the second programmed state;
program enabling all memory cells to be programmed to the second programmed state; and
applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the second programmed state, wherein programmed enable memory cells that verify at the second programmed state are subsequently inhibited for subsequent programming pulses.

17. The non-volatile memory circuit of claim 16 , wherein the initial state is an erased state.

18. The non-volatile memory circuit of claim 16 , wherein the array is formed according to a NAND type of architecture, each of the plurality of memory cells formed along the first word line being on a different NAND string of the array.

19. The non-volatile memory circuit of claim 16 , wherein the memory circuit is a monolithic two-dimensional semiconductor memory device in which the memory cells are arranged in single physical level above a silicon substrate.

20. The non-volatile memory circuit of claim 16 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and word lines, including the first word line, run in a horizontal direction

Assignees

• Sandisk Technologies Llc

Inventors

• Louie Kenneth
• Mui Man

Classifications

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title