Techniques for programming of select gates in NAND memory

Patent metadata

Field	Value
Publication number	US-9305648-B2
Application number	US-201414464122-A
Country	US
Kind code	B2
Filing date	Aug 20, 2014
Priority date	Aug 20, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

First claim

The invention claimed is:

1. A non-volatile semiconductor memory device, comprising:
a memory array structure including:
a first bit line;
a source line;
a first NAND string comprising:
a plurality of non-volatile memory cells connected in series between the source line and the first bit line;
one or more serially connected source select transistors through which the memory cells are connected to the source line; and
a plurality of serially connected drain select transistors through which the memory cells are connected to the first bit line, wherein the serially connected drain select transistors include a first drain select transistor and one or more second drain select transistors, wherein the second drain select transistors have a programmable threshold level and are connected to the first bit line through the first drain select transistor; and

read/write circuitry connectable to the first bit line, the source line, control gates of the memory cells, and control gates of the source select and drain select transistors, whereby the second drain select transistors are programmed by applying a sequence of one or more common programming pulses concurrently to the control gates of the second drain select transistors while the first bit line is initially set to a program enable level, the source line is set high, the control gates of the memory cells are set at a pass level, one or more of the source select transistors are turned off, and the first drain select transistor is turned on.

2. The non-volatile semiconductor memory device of claim 1 , wherein the second drain select transistors are further programmed by performing a verify operation subsequent to applying the sequence of pulses, wherein the second drain select transistors are commonly verified and, in response to verifying, the first bit line is set to a program inhibit level.

3. The non-volatile semiconductor memory device of claim 2 , wherein the program enable level is ground.

4. The non-volatile semiconductor memory device of claim 2 , wherein the program inhibit level is used in pre-charging bit lines by sense amp circuitry.

5. The non-volatile semionductor memory device of claim 2 , wherein the control gate of the first drain select transistor is set at a level to be turned on when the first bit line is at the program enable level and turned off when the first bit line is at the program inhibit level.

6. The non-volatile semiconductor memory device of claim 2 , wherein, in response to the verifying, the source line is set to a lower level.

7. The non-volatile semiconductor memory device of claim 1 , wherein the memory array structure further includes:
a plurality of additional bit lines and a corresponding plurality of additional NAND strings, each constructed similarly to the first NAND string and being connected between the source line and the corresponding additional bit line;
a plurality of word lines, each connected to the control gate of a corresponding one of the memory cells in each of the NAND strings;
one or more source select lines, each connected to the control gate of a corresponding one of the source select transistors in each of the NAND strings;
a first drain select line connected to the control gate of the first drain select transistor in each of the NAND strings; and
one or more second drain select lines, each connected to the control gate of a corresponding one of the second drain select transistors in each of the NAND strings;
wherein the read/write circuitry is further connectable to the additional bit lines, the source line, the word lines, the source select lines and the drain select lines, whereby the second drain select transistors of selected ones of the additional NAND strings are programmable concurrently with the first drain select transistor by applying the sequence of programming pulses to the second select lines, setting the word lines to the pass level, setting the source select lines to low, setting the first drain select line to high, and wherein the bit lines corresponding to the selected additional NAND strings are initially set to a program enable level, and
wherein the second drain select transistors are further programmed by performing a verify operation subsequent to the pulses of the sequence, wherein the second drain select transistors of each NAND string are commonly verified and, in response to verifying, the corresponding bit line is set to a program inhibit level.

8. The non-volatile semiconductor memory device of claim 7 , wherein when programming said second drain select transistors, the read/write circuitry initially concurrently enables adjacent bit lines; and, when programming the memory cells, the read/write circuitry does not concurrently enable the adjacent bit lines for programming.

9. The non-volatile semiconductor memory device of claim 1 , wherein the non-volatile semiconductor memory device is formed as a monolithic three-dimensional semiconductor memory device.

10. The non-volatile semiconductor memory device of claim 9 , wherein: the monolithic three-dimensional semiconductor memory device has a plurality of memory device levels vertically disposed above a silicon substrate, wherein said memory device levels have a plurality of the memory cells, each of which comprise a charge storage medium with a corresponding control gate horizontally disposed relative to said charge storage medium,
the memory cells in a memory device level are horizontally separated from each other and arranged in two or more horizontal rows of two or more memory cells,
at least one of said memory device levels have memory cells substantially vertically aligned with memory cells of a vertically adjacent memory device level, and
at least one control gate is common among at least two memory cells in one of said horizontal rows in one of said memory device levels and among at least two memory cells in a second one of said horizontal rows in said one of said memory device levels.

11. The non-volatile semiconductor memory device of claim 1 , wherein the number of second drain select transistors is greater than one.

12. A non-volatile semiconductor memory device, comprising:
a memory array structure including:
a first bit line;
a source line;
a first NAND string comprising:
a plurality of non-volatile memory cells connected in series between the source line and the first bit line;
one or more serially connected drain select transistors through which the memory cells are connected to the first bit line; and
a plurality of serially connected source select transistors through which the memory cells are connected to the source line, wherein the serially connected source select transistors include a first source select transistor and one or more second source select transistors, wherein the second source select transistors have a programmable threshold level and are connected to the source line through the first source select transistor; and

read/write circuitry connectable to the first bit line, the source line, control gates of the memory cells, and control gates of the source select and drain select transistors, whereby the second source select transistors are programmed by applying a sequence of one or more common programming pulses concurrently to the control gates of the second source select transistors while the first bit line is initially set to a program enable level, the source line is set to high, the control gates of the memory cells are set at a pass level, the first source select transistor is turned off, and the drain select transistors are turned on.

13. The non-volatile semiconductor memory device of claim 12 , wherein the second

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Nguyen Hao
• Mui Man
• Nguyen Khanh
• Lee Seungpil
• Ishigaki Toru
• Dong Yingda

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title