Optimized configurable NAND parameters

Patent metadata

Field	Value
Publication number	US-9229856-B2
Application number	US-201414452749-A
Country	US
Kind code	B2
Filing date	Aug 6, 2014
Priority date	Nov 29, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

First claim

It is claimed:

1. A method of operating a nonvolatile memory formed in two or more physical levels of memory cells disposed above a substrate comprising:
determining a first set of parameters to use in accessing a first plurality of memory cells in a first physical level based on at least one memory cell dimension of the first plurality of memory cells;
determining a second set of parameters to use in accessing a second plurality of memory cells in a second physical level based on the at least one memory cell dimension of the second plurality of memory cells, the second set of parameters including at least one parameter that is different from the first set of parameters;
subsequently accessing the first plurality of memory cells using the first set of parameters; and
accessing the second plurality of memory cells using the second set of parameters.

2. The method of claim 1 wherein the at least one memory cell dimension is a diameter of memory holes that extend through the plurality of physical levels of memory cells.

3. The method of claim 2 wherein the first plurality of memory cells are located in a lower physical level of the three-dimensional memory array, the second plurality of memory cells are located in an upper physical level of the three-dimensional memory array, and the diameter of the memory holes is greater in the second plurality of memory cells than in the first plurality of memory cells.

4. The method of claim 1 wherein the at least one parameter that is different is a voltage that is applied to program memory cells.

5. The method of claim 1 wherein the at least one parameter that is different is a number of voltage pulses used to program memory cells.

6. The method of claim 1 wherein the at least one parameter that is different is a read voltage that is used to read memory cells.

7. The method of claim 1 wherein the at least one parameter that is different is an erase voltage that is used to erase memory cells.

8. The method of claim 1 further comprising maintaining a write-erase cycle count for blocks of the nonvolatile memory and updating the first and second sets of parameters according to the write erase cycle counts.

9. The method of claim 8 further comprising updating the first set of parameters according to a first update scheme and updating the second set of parameters according to a second update scheme that is different from the first update scheme.

10. A nonvolatile memory system comprising:
a nonvolatile memory array formed in two or more physical levels of memory cells disposed above a substrate, each memory cell having a memory cell dimension, the memory cell dimension having a pattern of variation from physical level to physical level; and
memory access circuits that access memory cells of the array of memory cells according to access parameters, the memory access circuits having a first set of parameters for accessing a first plurality of memory cells of a first physical level and a second set of parameters for accessing a second plurality of memory cells of a second physical level, the second set of parameters including at least one parameter that is different from the first set of parameters.

11. The nonvolatile memory system of claim 10 wherein the nonvolatile memory system is a three-dimensional NAND memory array which includes a plurality of NAND strings that extend vertically in a direction that is perpendicular to a substrate surface to connect memory cells of the two or more physical levels.

12. The nonvolatile memory system of claim 11 wherein the pattern of variation is a pattern of variation of the memory cell dimension according to vertical distance from the substrate surface.

13. The nonvolatile memory system of claim 12 wherein the memory cell dimension is a diameter of an opening that extends vertically through word lines of the two or more physical levels with a channel extending vertically through the opening.

14. The nonvolatile memory system of claim 10 further comprising a write-erase cycle count circuit that maintains write-erase cycle counts for blocks in the nonvolatile memory system and updates access parameters according to write-erase cycle counts, the write-erase cycle count circuit formed on the substrate.

15. The nonvolatile memory system of claim 14 wherein the write-erase cycle count circuit has a first update scheme for updating the first set of parameters and a second update scheme for updating the second set of parameters.

16. The nonvolatile memory system of claim 10 wherein the memory access circuits have one or more additional sets of parameters for accessing additional memory cells of physical levels other than the first and second physical levels.

Assignees

• Sandisk Technologies Inc

Inventors

• Avila Chris
• Dong Yingda
• Mui Man

Classifications

• G11C11/5621 Primary

  using charge storage in a floating gate · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title