Programming techniques for non-volatile memories with charge trapping layers

Patent metadata

Field	Value
Publication number	US-9947395-B2
Application number	US-201715486512-A
Country	US
Kind code	B2
Filing date	Apr 13, 2017
Priority date	Mar 2, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

First claim

What is claimed is:

1. A method, comprising:
programming a group of memory cells connected to a word line in parallel by applying a programming voltage in a series of programming pulses to the word line, wherein programming the group of memory cells further comprises:
program-enabling a first subset of the group of memory cells;
program-inhibiting a second subset of the group of memory cells;

identifying a number of memory cells that remain program-enabled after a first programming pulse; and
adjusting a timing of a second programming pulse in response to the number of memory cells that remain program-enabled after the first programming pulse, wherein adjusting the timing includes adjusting a rise time and a fall time of the second programming pulse, and wherein adjusting the timing reduces the overall programming time of the group of memory cells.

2. The method of claim 1 , further comprising changing one or more memory cells of the first subset of the group of memory cells that are program-enabled to be program-inhibited after completion of the program-enabling of the first subset of the group of memory cells.

3. The method of claim 1 , wherein each of the programming pulses is identified with a pulse number that increases with each subsequent instance of the programming pulses.

4. The method of claim 3 , wherein as the pulse number increases, the number of memory cells of the first subset of the group of memory cells that are program-enabled decreases and a number of the second subset of the group of memory cells that are program-inhibited increases.

5. The method of claim 4 , wherein, as the number of memory cells of the first subset of the group of memory cells that are program-enabled decreases, the timing of each of the programming pulses decreases.

6. The method of claim 4 , wherein, as the number of memory cells of the first subset of the group of memory cells that are program-enabled decreases, a time constant of the word line decreases, and as the time constant decreases, the timing of each of the programming pulses decreases.

7. The method of claim 6 , wherein the time constant is computed as a product of an effective capacitance of the word line and a resistance of the word line, and wherein the effective capacitance is a sum of a capacitance of the word line and a capacitance of the first subset of the group of memory cells that are program-enabled.

8. The method of claim 6 , wherein the time constant decreases based upon a decrease in an effective capacitance of the word line as the number of memory cells of the first subset of the group of memory cells that are program-enabled decreases.

9. The method of claim 1 , wherein a word line driver of a programming circuit applies the programming voltage to the word line.

10. The method of claim 9 , wherein the word line applies the programming voltage to an access node connected to the word line.

11. A memory comprising:
a plurality of memory cells connected to a word line, wherein each of the plurality of memory cells is either program-enabled or program-inhibited;
a programming circuit having a word driver connected to the word line via an access node; and
control circuitry connected to the programming circuit, wherein the control circuitry causes the word driver to output a programming voltage on the word line through the access node, wherein the programming voltage is associated with a programming pulse having a timing value, and wherein the timing value in the programming pulse is based upon a relative number of the program-enabled memory cells and the program-inhibited memory cells.

12. The memory of claim 11 , wherein the number of the program-enabled memory cells decreases and the number of the program-inhibited memory cells increases as a number of the programming pulse increases.

13. The memory of claim 12 , wherein the control circuitry computes the timing value using a time constant of the word line, and wherein as the number of the program-enabled memory cells decreases, the time constant decreases and the timing value decreases.

14. The memory of claim 13 , wherein the timing constant is a function of an effective capacitance of the word line that is computed as a sum of a capacitance of the word line and a capacitance of all of the program-enabled memory cells, and wherein the effective capacitance decreases as the number of the program-enabled memory cells decreases.

15. A method, comprising:
programming, by a programming circuit, a group of memory cells in parallel by applying a programming voltage with a series of programming pulses and increasing voltage level through a word line, wherein the word line is connected to the group of memory cells;
receiving, by a control circuitry, a determination of a number of program-enabled memory cells and program-inhibited memory cells in the group, wherein the number of the program-enabled memory cells increases and the number of the program-inhibited memory cells decreases as a number associated with the programming pulses increases; and
adjusting, by the control circuitry, a timing of each of the programming pulses based upon a number of the program-enabled memory cells to be programmed with that programming pulse, wherein as the number of the program-enabled memory cells decreases, the timing of the programming pulses decreases.

16. The method of claim 15 , wherein the programming voltage is applied to the word line by a word line driver connected to the word line via an access node.

17. The method of claim 15 , wherein as the number of the program-enabled memory cells decreases, an effective capacitance of the word line decreases.

18. The method of claim 17 , wherein as the effective capacitance decreases, a time constant of the word line decreases, causing a decrease in the timing of the programming pulses.

19. The method of claim 15 , wherein a resistance of the word line is substantially constant.

20. The method of claim 15 , further comprising adjusting the timing of each of the programming pulses until all of the memory cells become program-inhibited.

Assignees

• Sandisk Technologies Llc

Inventors

• Louie Kenneth
• Mui Man

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5671 Primary

  using charge trapping in an insulator · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title