Back gate operation with elevated threshold voltage

Patent metadata

Field	Value
Publication number	US-9240238-B2
Application number	US-201314033100-A
Country	US
Kind code	B2
Filing date	Sep 20, 2013
Priority date	Sep 20, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.

First claim

It is claimed:

1. A method comprising:
applying a first set of programming conditions that includes applying a first back gate voltage to a back gate of a block for programming operations during a first period of operation;
performing one or more back gate tuning operations on the back gate, the back gate tuning operation configured to set a threshold voltage of a back gate transistor to be in a target range;
subsequently determining that the threshold voltage of the back gate transistor remains higher than the target range after performing the back gate tuning operations; and
subsequently, replacing the first set of programming conditions with a second set of programming conditions that includes applying a second back gate voltage to the back gate of the block for programming operations during a second period of operation, the second back gate voltage being larger than the first back gate voltage.

2. The method of claim 1 wherein the first back gate voltage is applied to the back gate when programming one or more word lines near the back gate that are located between the back gate and a source line during the first period of operation.

3. The method of claim 2 wherein the second back gate voltage is applied to the back gate when programming the one or more word lines near the back gate that are located between the back gate and the source line, during the second period of operation.

4. The method of claim 1 wherein the first set of programming conditions are maintained for as long as the threshold voltage of the back gate transistor is found to be within the target range immediately after a back gate tuning operation.

5. The method of claim 1 further comprising: performing one or more back gate tuning operations on the back gate of the block to maintain threshold voltage of the back gate in a modified target range during the second period of operation.

6. The method of claim 5 further comprising: subsequently determining that the threshold voltage of the back gate transistor remains higher than the modified target range after back gate tuning; and
subsequently, replacing the second set of programming conditions with a third set of programming conditions that includes a third back gate voltage that is applied to the back gate of the block for programming operations during a third period of operation, the third back gate voltage being larger than the second back gate voltage.

7. The method of claim 6 wherein the first back gate voltage is insufficient to turn on back gate transistors with threshold voltages within the modified target range, and the second back gate voltage is insufficient to turn on back gate transistors with threshold voltages higher than the modified target range.

8. The method of claim 1 wherein the first set of programming conditions is optimized to produce a low Bit Error Rate (BER) in a new memory array and the second set of programming conditions is not optimized to produce a low BER in a new memory.

9. The method of claim 8 wherein the second set of programming conditions allows programming of data along word lines that cannot be programmed using the first set of programming conditions after a period of use of the memory array.

10. An apparatus comprising:
a back gate control circuit configured to apply a default set of programming conditions that includes a first back gate voltage that is applied to a back gate of the block for programming cells along word lines near the back gate during a first period of operation;
a threshold voltage resolving circuit configured to determine if the threshold voltages of back gate transistors are higher than a target range; and
the back gate control circuit further configured to replace the default set of programming conditions with a modified set of programming conditions that includes a second back gate voltage that is applied to the back gate of the block for programming cells along word lines near the back gate during a second period of operation, the second back gate voltage being larger than the first back gate voltage.

11. The apparatus of claim 10 wherein the first back gate voltage is sufficient to turn on back gate transistors that have threshold voltages within the target range and is insufficient to turn on back gate transistors that have threshold voltages higher than the target range.

12. The apparatus of claim 11 wherein the second back gate voltage is sufficient to turn on back gate transistors that have threshold voltages higher than the target range.

13. The apparatus of claim 10 wherein the back gate control circuits are further configured to perform one or more back gate transistor threshold voltage modification operations to maintain threshold voltage of back gate transistors within the target range.

14. The apparatus of claim 10 wherein the back gate control circuits are further configured to identify a pattern of programming failures when programming word lines near the back gate that are located between the back gate and a source line prior to replacing the default set of programming conditions.

15. A system comprising:
a plurality of NAND strings that individually include two wings that each extend in a direction perpendicular to a surface of a substrate, the two wings connected by a back gate transistor;
a back gate configured to form a common gate terminal for each back gate transistor of a block; and
a back gate control circuit configured to control a voltage applied to the back gate, the back gate control circuit configured to supply a first boosting voltage to the back gate during a first plurality of memory cell programming operations and configured to subsequently supply a second boosting voltage to the back gate during a second plurality of memory cell programming operations, the second boosting voltage being higher than the first boosting voltage.

16. The system of claim 15 wherein the back gate control circuit is configured to supply the first and second boosting voltages to the back gate during programming of word lines near the back gate that are between the back gate and a source terminal.

17. The system of claim 15 further comprising a back gate threshold voltage modification circuit that is configured to modify threshold voltages of back gate transistors.

18. The system of claim 17 further comprising a back gate threshold voltage resolving circuit that is configured to resolve threshold voltages of back gate transistors.

Assignees

• Sandisk Technologies Inc

Inventors

• Raghu Deepak
• Dusija Gautam
• Avila Chris
• Dong Yingda
• Mui Man

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title