Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

Patent metadata

Field	Value
Publication number	US-9633742-B2
Application number	US-201414328018-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

First claim

It is claimed:

1. A non-volatile memory circuit, comprising:
an array of non-volatile memory cells formed as a plurality of blocks;
a plurality of bit lines spanning the plurality of blocks to which the memory cells of the blocks are connected; and
sensing circuitry connected to the array, including a plurality of sense amp circuits connected to the bit lines, wherein the sensing circuitry varies a time allotted for biasing the array for a sensing operation of selected memory cells based upon a physical distance along the bit lines from the sense amp circuits to the block of the selected memory cells,
wherein:
each of the blocks belongs to one of a plurality of block groups,
each of the block groups contains one or more adjacent blocks of the array,
the blocks of a group use a shared time allotment for biasing the array for the sensing operations of selected memory cells belonging thereto,
the different block groups use different time allotments for biasing the array for the sensing operations of selected memory cells belonging thereto, and
block groups that are physically closer to corresponding ones of the sense amp circuits along the bit lines than others of the block groups are biased for shorter time allotments than the others of the block groups to reduce total power expended during the biasing.

2. The non-volatile memory circuit of claim 1 , wherein the shared timings of the different block groups differ from each other by an offset.

3. The non-volatile memory circuit of claim 2 , wherein initial values for the offsets are based upon device characterization tests.

4. The non-volatile memory circuit of claim 2 , wherein initial values for the offsets are set prior to the memory circuit being supplied to a user.

5. The non-volatile memory circuit of claim 4 , wherein one or more of the offsets are changed after the non-volatile memory circuit has aged.

6. The non-volatile memory circuit of claim 1 , wherein the different time allotments vary in a number of clock cycles allotted for a phase of the sensing operation.

7. The non-volatile memory circuit of claim 6 , wherein the phase of the sensing operation is a pre-charge operation.

8. The non-volatile memory circuit of claim 1 , wherein the sensing operation is a data read.

9. The non-volatile memory circuit of claim 1 , wherein the sensing operation is a program verify.

10. The non-volatile memory circuit of claim 1 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

11. A method, comprising:
receiving at a non-volatile memory circuit a command that includes a sensing operation for one or more selected memory cells, the memory circuit including an array of non-volatile memory cells formed as a plurality of multi cell erase blocks with a plurality of bit lines to which the memory cells of the blocks are connected spanning the plurality of erase blocks and having a plurality of sense amp circuits connected to the bit lines;
determining the erase block to which the selected memory cells belong; and
allotting time for biasing the array for the sensing operation based upon a physical distance along the bit lines from the determined block to the sense amp circuits,
wherein:
the memory circuit configures each of the blocks belonging to one of a plurality of block groups,
each of the block groups contains one or more adjacent blocks of the array,
the blocks of a group use a shared time allotment for the sensing operation of selected memory cells belonging thereto,
the different groups use different time allotments for the sensing operation of selected memory cells belonging thereto,
determining the erase block to which the selected memory cells belong comprises determining the block group to which the determined block belongs,
allotting time includes selecting the time allotment for the block group to which the determined block belongs, and
allotting time further includes allotting less time for biasing block groups that are physically closer to the corresponding sense amp circuits along the bit lines than for biasing block groups that are physically further from the corresponding sense amp circuits to conserve power.

12. The method of claim 11 , wherein the time allottments of different block groups differ from each other by an offset.

13. The method of claim 12 , wherein the offsets are settable parameters.

14. The method of claim 12 , wherein the offsets differ by a number of clock cycles.

15. The method of claim 11 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

16. A non-volatile memory circuit, comprising:
an array of non-volatile memory cells formed as a plurality of multi cell erase blocks;
a bit line spanning the plurality of erase blocks to which the memory cells of the blocks are connected;
logic circuitry configured to allot time for biasing the array for sensing operations; and
sensing circuitry connected to the array, including a plurality of sense amp circuits connected to the bit line and the logic circuitry, wherein the sensing circuitry is configured to allot time for biasing the array for the sensing operations of selected memory cells proportionally to a physical distance along the bit line from the sense amp circuits to the block that includes the selected memory cells to expend less power biasing selected memory cells that are physically closer to the sense amp circuits than for biasing selected memory cells that are physically further from the sense amp circuits,
wherein:
each of the blocks belongs to one of a plurality of block groups,
each of the block groups contains one or more adjacent blocks of the array,
the blocks of a group use a shared timing for the sensing operation of selected memory cells belonging thereto,
different block groups use different timings for the sensing operation of selected memory cells belonging thereto.

17. The non-volatile memory circuit of claim 16 , wherein the time allotments of the different block groups differ from each other by an offset.

18. The non-volatile memory circuit of claim 16 , wherein the sensing circuitry is configured to vary time allotments for biasing the array during the sensing operations based on coupling between the bit line and conductors within the array.

Assignees

• Sandisk Technologies Llc

Inventors

• Desai Amul Dhirajbhai
• Nguyen Hao
• Lee Seungpil
• Mui Man

Classifications

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• H01L27/11582

  Electricity · mapped topic