Utilizing NAND strings in dummy blocks for faster bit line precharge

Patent metadata

Field	Value
Publication number	US-9595338-B2
Application number	US-201414495283-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Sep 24, 2014
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

First claim

It is claimed:

1. A method of operating a non-volatile memory circuit, the method comprising:
performing a sensing operation on a non-volatile memory circuit having a plurality of bit lines, by each of which a corresponding plurality of individually selectable NAND strings are connectable to an associated sense amp circuit, the NAND stings each comprising a plurality of memory cells connected in series between the corresponding bit line and a source line, the sensing operation including a pre-charge phase, wherein the pre-charge phase includes:
pre-charging each bit line of a set of one or more bits lines by the associated sense amp circuits; and
concurrently pre-charging each bit line of the set of bit lines from the source line through one or more of the corresponding NAND strings connected thereto,

wherein the sensing operation is part of a write operation, the pre-charge phase being performed as part of a transition between a pulse operation and a subsequent verify operation.

2. The method of claim 1 , wherein the NAND strings used to pre-charge the set of bit lines are non-selected for the sensing operation.

3. The method claim 2 , wherein the NAND strings used to pre-charge the set of bit lines are not assigned by the memory circuit for the storage of data.

4. The method of claim 3 , wherein the memory cells along the NAND strings used to pre-charge the set of bit lines are in an erased state.

5. The method of claim 1 , wherein the write operation further comprises:
an additional pulse operation subsequent to the verify operation; and
a verify to pulse pre-charge operation, including:
pre-charging each of one or more of the set bits lines by the associated sense amp circuits; and
concurrently pre-charging each of said one or more of the set of bit lines by one or more of the corresponding NAND strings connected thereto from the source line.

6. The method of claim 1 , wherein the pre-charge phase is performed to discharge the set of bit lines.

7. The method of claim 1 , wherein the NAND strings are formed as a plurality of blocks, each of the blocks having one or more NAND strings connected between each of the bit lines and a common source line.

8. The method of claim 7 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

9. The method of claim 8 , wherein for each of the NAND strings the memory cells are connected in series between one or more source select gates and one or more drain select gates, the memory cells being connected along word lines and the source and drain select gates being respectively connected along source and drain select lines, the NAND strings being formed above a P well and each connected, though the corresponding drain select gates, to the associated bit line, and
wherein the NAND strings run in a vertical direction relative to the substrate, and the word lines, and source and drain select lines, and bit lines run in a horizontal direction relative to the substrate.

10. The method of claim 7 , wherein each of the blocks has a plurality of sub-divisions each with a single NAND string of the block's NAND strings connected between each of the bit lines and the common source line, the NAND strings of the sub-divisions being individually selectable.

11. The method claim 7 , wherein the NAND strings used to pre-charge the set of bit lines belong to blocks not assigned by the memory circuit for the storage of data.

12. The method of claim 11 , wherein the memory cells of the blocks not assigned by the memory circuit for the storage of data containing the NAND strings used to pre-charge the set of bit lines are in an erased state.

13. A memory circuit, comprising:
sensing circuitry, including a plurality of sense amp circuits;
an array of non-volatile memory cells having a plurality of bit lines connected to individually selectable NAND stings each comprising a plurality of memory cells connected in series between the corresponding bit line and a source line; and
driver circuitry selectively connectable to the source lines,
wherein the sense amp circuits are configured to pre-charge each bit line using an associated sense amp circuits as part of a sensing operation, and wherein the driver circuitry is configured to concurrently pre-charge each bit line by way of the source line, and
wherein the sensing operation is part of a write operation, the pre-charge being performed as part of a transition between a pulse operation and a subsequent verify operation.

14. The memory circuit of claim 13 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

15. The memory circuit of claim 13 , wherein the NAND strings are formed as a plurality of blocks, each of the blocks having one or more NAND strings connected between each of the bit lines and a common source line, and
wherein the NAND strings used to pre-charge the set of bit lines belong to blocks not assigned by the memory circuit for the storage of data.

16. A memory circuit, comprising:
sensing circuitry, including a plurality of sense amp circuits;
an array of non-volatile memory cells having a plurality of bit lines connected to individually selectable NAND stings each comprising a plurality of memory cells connected in series between the corresponding bit line and a source line; and
driver circuitry selectively connectable to the source lines,
wherein the memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium,
wherein the NAND strings are formed as a plurality of blocks, each of the blocks having one or more NAND strings connected between each of the bit lines and a common source line,
wherein the NAND strings used to pre-charge the set of bit lines belong to blocks not assigned by the memory circuit for the storage of data, and
wherein the sense amp circuits are configured to pre-charge each bit line using an associated sense amp circuits as part of a sensing operation, and wherein the driver circuitry is configured to concurrently pre-charge each bit line by way of the source line, and
wherein the sensing operation is part of a write operation, the pre-charge being performed as part of a transition between a pulse operation and a subsequent verify operation.

Assignees

• Sandisk Technologies Llc

Inventors

• Lee Juan Carlos
• Nguyen Hao
• Mui Man
• Kuo Tien-Chien
• Mizutani Yuki

Classifications

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title