Techniques for programming of select gates in NAND memory

Patent metadata

Field	Value
Publication number	US-9947407-B2
Application number	US-201715599850-A
Country	US
Kind code	B2
Filing date	May 19, 2017
Priority date	Aug 20, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

First claim

What is claimed is:

1. A method of programming non-volatile memory, comprising:
applying a program enable voltage to a bit line;
applying a pass voltage to a control gate of each of a plurality of non-volatile memory cells coupled to the bit line through a plurality of serially-connected drain select transistors including a first drain select transistor and two or more second drain select transistors; and
applying the pass voltage to a control gate of the first drain select transistor while applying a program voltage to a control gate of each of the second drain select transistors to concurrently program the second drain select transistors independently of the first drain select transistor.

2. The method of claim 1 , wherein:
applying the pass to the control gate of the first drain select transistor comprises applying a conducting voltage level to a first control line coupled to the control gate of the first drain select transistor; and
applying the program voltage to the control gate of each of the second drain select transistors comprises applying the program voltage to a second control line coupled to the control gate of each of the second drain select transistors.

3. The method of claim 2 , wherein:
the second drain select transistors have programmable threshold voltages.

4. The method of claim 3 , wherein:
the first drain select transistor is coupled to the bit line and the two or more second drain select transistors are coupled to the bit line via the first drain select transistor.

5. The method of claim 3 , wherein:
the threshold voltages of the second drain select transistors are jointly programmable; and
the first drain select transistor is directly coupled to the bit line without an intervening transistor.

6. The method of claim 3 , wherein the threshold voltages of the second drain select transistors are configured to have positive values.

7. The method of claim 2 , further comprising:
programming the plurality of non-volatile memory cells by biasing the second control line at a voltage level below the threshold voltages of the second drain select transistors.

8. The method of claim 1 , further comprising:
turning off a first source select transistor coupled to the plurality of non-volatile memory cells while applying the program enable level to the bit line.

9. The method of claim 8 , wherein:
the first source select transistor is coupled to a source line and a second source select transistor is coupled to the source line via the first source select transistor;
a control gate of the first source select transistor is controllable separately from a control gate of the second source select transistor; and
the method further comprises turning on the second source select transistor while concurrently programming the second drain select transistors.

10. The method of claim 2 , wherein the plurality of serially-connected drain select transistors is a first plurality of serially-connected drain select transistors, the plurality of non-volatile memory cells is a first plurality of non-volatile memory cells, and the bit line is a first bit line, the non-volatile memory further comprises:
a second plurality of serially-connected drain select transistors each having a control gate; and
a second plurality of non-volatile memory cells coupled to a second bit line through the second plurality of serially-connected drain select transistors,
wherein the second plurality of serially-connected drain select transistors comprises a third drain select transistor coupled to the second bit line and two or more fourth drain select transistors coupled to the second bit line via the third drain select transistor,
wherein the control gate of the third drain select transistor is coupled to the first control line and the control gates of the fourth drain select transistors are coupled to a third control line and
wherein the method further comprises concurrently programming the fourth drain select transistors independently of the third drain select transistor.

11. A method of programming non-volatile memory, comprising:
providing a first drain select transistor coupled to a bit line and two or more second drain select transistors coupled to the bit line via the first drain select transistor, the first drain select transistor is coupled to a first control line and the second drain select transistors are coupled to a second control line, the second drain select transistors having programmable threshold voltages;
providing a plurality of memory transistors coupled to the first and second drain select transistors;
providing one or more source select transistors coupled to the plurality of memory transistors; and
concurrently programming the two or more second drain select transistors independently of the first drain select transistor.

12. The method of claim 11 , wherein:
each second drain select transistor has a programmable threshold voltage; and
concurrently programming the two or more second drain select transistors comprises jointly programming the threshold voltages of the two or more second drain select transistors.

13. The method of claim 12 , wherein concurrently programming the two or more second drain select transistors comprises:
applying a conducting voltage level to the first control line; and
applying a program voltage to the second control line.

14. The method of claim 13 , wherein:
concurrently programming the two or more second drain select transistors comprises programming the threshold voltages of the two or more second drain select transistors independently from a threshold voltage of the first drain select transistor.

15. The method of claim 11 , wherein concurrently programming the two or more second drain select transistors comprises:
setting the bit line to a program enable level;
setting a source line coupled to the one or more source select transistors to a high level;
setting a control gate of each of the memory transistors to a pass level; and
turning off the one or more source select transistors.

16. The method of claim 15 , further comprising:
commonly verifying the two or more second drain select transistors subsequent to concurrently programming;
setting the bit line to a program inhibit level in response to successfully verifying the two or more second drain select transistors; and
setting the source line to a low level in response to successfully verifying the two or more second drain select transistors.

17. The method of claim 16 , wherein:
each of the second drain select transistors comprises a control gate; and
the method further comprises setting the control gate of the first drain select transistor at a level to be turned on when the bit line is at the program enable level and turned off when the bit line is at the program inhibit level.

18. A method of programming non-volatile memory, comprising:
applying a program enable level to a bit line;
applying a pass voltage to a control gate of each of a plurality of non-volatile memory cells coupled to a source line through a plurality of serially-connected source select transistors including a first source select transistor and two or more second source select transistors; and
concurrently programming the second source select transistors independently of the first source select transistor by turning off the first source select transistor while applying a program voltage to a control gate of each of the second source select transistors.

19. The method of claim 18 , further comprising:
applying the pass voltag

Assignees

• Sandisk Technologies Llc

Inventors

• Nguyen Hao
• Mui Man
• Nguyen Khanh
• Lee Seungpil
• Ishigaki Toru
• Dong Yingda

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• H01L27/11556

  Electricity · mapped topic

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• H01L27/11582

  Electricity · mapped topic