Zoned erase verify in three dimensional nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9312026-B2
Application number	US-201414466786-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Aug 22, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.

First claim

It is claimed:

1. A method of operating blocks of memory cells in a block-erasable NAND flash memory comprising:
performing a block erase operation that applies an erase voltage to all word lines of the block;
subsequently performing a block erase verify operation to determine if the block erase operation was successful;
in response to determining that the block erase operation was not successful performing a sub-block erase verify operation that applies an erase verify voltage to a first subset of word lines of the block and does not apply the erase verify voltage to a second subset of word lines of the block to determine if the block erase operation successfully erased the first subset of word lines; and
if the sub-block erase verify operation indicates that the first subset of word lines is erased then designating the first subset of word lines as a good subset for subsequent storage of data.

2. The method of claim 1 wherein the sub-block erase verify operation applies additional erase verify voltages to the first subset of word lines of the block to obtain a distribution of threshold voltages of the sub-block.

3. The method of claim 1 wherein the first subset of word lines of the block consists of one word line and the erase verify voltage is a read voltage, and all other word lines of the block receive a read pass voltage.

4. The method of claim 1 further comprising: performing one or more additional sub-block erase verify operations to identify other subsets of word lines of the block for designation as good subsets for subsequent storage of data.

5. The method of claim 4 further comprising: if the sub-block erase verify operation or an additional sub-block erase verify operation indicates that a corresponding subset of word lines is not erased then designating the corresponding subset of word lines as a bad subset that is not good for subsequent storage of data.

6. The method of claim 4 wherein the one or more additional sub-block erase verify operations are performed for subsets that include all word lines of the block so that the entire block is mapped into subsets and each subset is either designated as being a good subset for subsequent storage of data or as a bad subset that is not for subsequent storage of data.

7. The method of claim 6 wherein each subset is an individual word line that is subject to a separate sub-block erase verify and is individually designated as a good word line for subsequent storage of data or as a bad word line that is not for subsequent storage of data.

8. The method of claim 6 wherein each subset is a plurality of word lines that is subject to a separate sub-block erase verify and is individually designated as a good plurality of word lines for subsequent storage of data or as a bad plurality of word lines for subsequent storage of data.

9. The method of claim 8 wherein word lines of the block are divided into subsets in zones based on physical location, zones consisting of equal numbers of neighboring word lines.

10. The method of claim 9 wherein the block-erasable NAND flash memory is a monolithic three-dimensional semiconductor memory device comprising a plurality of memory device levels vertically disposed above a silicon substrate and word lines of the block are divided into zones based on respective vertical levels with respect to the underlying substrate.

11. The method of claim 10 wherein driver circuits for accessing the block-erasable NAND flash memory are also disposed on the silicon substrate.

12. A method of operating a block of memory cells in a monolithic three-dimensional block-erasable memory device that has a plurality of device levels vertically disposed above a silicon substrate comprising:
performing a block erase operation that applies an erase voltage to word lines in all of the plurality of memory device levels of the block;
subsequently performing a block erase verify operation to determine if the block erase operation was successful;
in response to determining that the block erase operation was not successful performing a series of sub-block erase testing operations that apply an erase verify voltage to word lines of a selected sub-block of the block while not applying the erase verify voltage to word lines of unselected sub-blocks of the block to verify if word lines of the selected sub-block are erased;
subsequently mapping each of the sub-blocks as either a good sub-block or a bad sub-block according to the results of the sub-block testing operations; and
subsequently storing user data in good sub-blocks while prohibiting storage of user data in bad sub-blocks.

13. The method of claim 12 wherein the block includes a plurality of sets of strings, each set of strings comprising vertical NAND strings that share word lines, and further comprising individually performing erase testing on a first set of strings by applying an erase voltage to word lines of the first set of strings while not applying the erase verify voltage to word lines of unselected sets of strings.

14. The method of claim 13 further comprising individually performing erase testing on each set of strings of the block and designating any set of strings that fails erase testing as a bad set of strings that is not good for subsequent storage of data.

15. The method of claim 12 further comprising configuring the bad sub-blocks by raising threshold voltages of memory cells of the bad-sub blocks above an erased level.

16. The method of claim 15 further comprising subsequently repeating the configuring of the bad sub-blocks at intervals based on write-erase cycle count of the block.

17. The method of claim 12 further comprising applying different voltages to word lines of good sub-blocks and bad sub-blocks during subsequent memory access operations.

18. The method of claim 17 wherein applying different voltages includes applying an erase voltage to word lines of good sub-blocks during subsequent erase operations while applying a voltage that is lower than the erase voltage to word lines of bad sub-blocks.

19. The method of claim 17 wherein applying different voltages includes at least one of: applying a different read pass voltage, or applying a different write pass voltage, or applying a different boosting voltage.

20. A monolithic block-erasable three-dimensional semiconductor memory device formed in multiple physical levels of memory elements disposed above a silicon substrate comprising:
a first plurality of blocks that pass block erase testing and are designated for block erase in which an erase voltage is applied to word lines of all physical levels of the block at the same time; and
a second plurality of blocks that fail block erase testing and subsequently pass sub-block erase testing and are configured for sub-block operation in which at least one sub-block that includes a plurality of word lines is designated as a bad sub-block and is not used to store user data while at least one other sub-block that includes a plurality of word lines is designated as a good sub-block and is used to store user data.

21. The monolithic block-erasable three-dimensional semiconductor memory device of claim 20 wherein word lines of a block of the second plurality of blocks are divided into sub-blocks according to their physical level with respect to the silicon substrate.

22. The monolithic block-erasable three-dimensional semiconductor memory device of claim 20 further comprising driver circuitry associated with one or more of said memory elemen

Assignees

• Sandisk Technologies Inc

Inventors

• Kochar Mrinal
• Dusija Gautam
• Avila Chris
• Dong Yingda
• Mui Man
• Huang Yichao
• Raghu Deepak

Classifications

• G11C16/3445 Primary

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C2216/18

  Flash erasure of all the cells in an array, sector or block simultaneously · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title