Multi tier three-dimensional memory devices including vertically shared bit lines

Patent metadata

Field	Value
Publication number	US-9502471-B1
Application number	US-201514834943-A
Country	US
Kind code	B1
Filing date	Aug 25, 2015
Priority date	Aug 25, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

First claim

What is claimed is:

1. A multi-tier memory device, comprising:
a first tier overlying a substrate and comprising a first alternating stack of first insulating layers and first electrically conductive layers, and first vertical transistors each including a first semiconductor channel and a first-tier top active region that contacts an upper end of the first semiconductor channel;
bit lines overlying the first tier and electrically shorted to respective first-tier top active regions; and
a second tier overlying the bit lines and comprising a second alternating stack of second insulating layers and second electrically conductive layers, and second vertical transistors each including a second semiconductor channel and a second-tier bottom active region that contacts a lower end of the second semiconductor channel,
wherein the bit lines are electrically shorted to respective second-tier bottom active regions.

2. The multi-tier memory device of claim 1 , wherein:
each first semiconductor channel is located within a respective first memory stack structure that extends through the first alternating stack; and
each second semiconductor channel is located within a respective second memory stack structure that extends through the second alternating stack.

3. The multi-tier memory device of claim 2 , wherein:
the first-tier top active regions are first-tier drain regions; and
the second-tier bottom active regions are second-tier drain regions.

4. The multi-tier memory device of claim 3 , wherein:
each bit line is electrically shorted to respective first-tier drain regions through at least one first drain-side interconnect structure extending through a dielectric material layer in the first tier, and is electrically shorted to respective second-tier drain regions through at least one second drain-side interconnect structure extending through another dielectric material layer overlying the bit lines;
sidewalls of the second-tier drain regions contact a dielectric material layer; and
each of the second-tier drain regions comprises a doped semiconductor region that contacts an underlying metal-semiconductor alloy region.

5. The multi-tier memory device of claim 3 , wherein:
the substrate comprises a substrate semiconductor layer;
the substrate semiconductor layer comprises first-tier source regions and horizontal channels extending between a respective first-tier source region and a respective subset of first semiconductor channels;
the second tier comprises second-tier source regions contacting an upper end of a respective second semiconductor channel; and
the second tier comprises a source line that is electrically shorted to the second-tier source regions.

6. The multi-tier memory device of claim 5 , further comprising:
first source contact via structures extending through the first alternating stack and contacting the first-tier source regions;
second source contact via structures extending through the second alternating stack and contacting the source line; and
interconnect structures and electrically shorting respective pairs of the first source contact via structures and the second source contact via structures.

7. The multi-tier memory device of claim 2 , wherein each of the first and second memory stack structures comprises, from outside to inside:
at least one blocking dielectric,
a memory material layer,
a tunneling dielectric, and
one of a first semiconductor channel and a second semiconductor channel.

8. The multi-tier memory device of claim 2 , further comprising:
a third tier overlying the second tier and comprising a third alternating stack of third insulating layers and third electrically conductive layers, third memory stack structures extending through the third alternating stack and each including a third semiconductor channel, and third drain regions contacting an upper end of each third semiconductor channel; and
a source line located between the second tier and the third tier and electrically shorted to a subset of second-tier source regions contacting an upper end of a respective second semiconductor channel and to a subset of third source regions contacting a lower end of a respective third semiconductor channel.

9. The multi-tier memory device of claim 2 , further comprising:
an epitaxial pedestal in epitaxial alignment with a semiconductor material layer within the substrate, vertically extending between the substrate and a topmost tier within the multi-tier memory device, and including peripheral semiconductor devices at a level of the topmost tier;
a first retro-stepped dielectric material portion overlying first stepped surfaces of the first alternating stack; and
a second retro-stepped dielectric material portion overlying second stepped surfaces of the second alternating stack.

10. The multi-tier memory device of claim 1 , wherein the multi-tier memory device comprises a vertical NAND device located over the substrate.

11. The multi-tier memory device of claim 10 , wherein:
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels including the first and second semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

12. The multi-tier memory device of claim 1 , further comprising:
a plurality of first local bit line pillar structures that extend parallel to a stacking direction of the first alternating stack and located below each respective first semiconductor channel;
a plurality of second local bit line pillar structures that extend parallel to a stacking direction of the second alternating stack and located above each respective second semiconductor channel;
a first resistive memory material layer located on a sidewall of the first alternating stack; and
a second resistive memory material layer located on a sidewall of the second alternating stack.

13. The multi-tier memory device of claim 12 , wherein:
each first vertical transistor includes a first-tier bottom active region that is electrically shorted to a respective first local bit line pillar structure;
each second vertical transistor includes a second-tier top active region that is electrically shorted to a respective second local bit line pillar structure; and
the multi-tier memory device is a resistive random access memory device in which the first and second electrically conductive layers are word lines for accessing a resistive memory element within a three-dimensional array of resistive memory elements.

14. A method of manufac

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lu Zhenyu
• Chien Henry
• Alsmeier Johann
• Miyata Koji
• Zhang Tong
• Mui Man
• Kai James
• Shi Wenguang
• Zhao Wei
• Hu Xiaolong
• Xu Jiyin
• Hemink Gerrit Jan
• Petti Christopher

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title