Method of making 3D memory stacking formation with high circuit density
US-12598734-B2 · Apr 7, 2026 · US
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Gardner Mark I patents
Gardner Mark I is listed as an inventor on 279 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gardner Mark I |
| Total patents | 279 |
| First publication | Nov 19, 2020 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Electrical energy produced by rotating magnets
US-2026088690-A1 · Mar 26, 2026 · US
Device and method for determining wafer bow
US-12581898-B2 · Mar 17, 2026 · US
Contactless wafer positioning carrier design
US-2026060040-A1 · Feb 26, 2026 · US
Transistor stacking by wafer bonding
US-12543369-B2 · Feb 3, 2026 · US
3D high density self-aligned nanosheet device formation with efficient layout and design
US-12538520-B2 · Jan 27, 2026 · US
Metal recess depth measurements by capacitor test structure
US-2026022929-A1 · Jan 22, 2026 · US
Method for selective exposure of wafer to corrective irradiation at a per-die level
US-12529965-B2 · Jan 20, 2026 · US
Three-dimensional plurality of n horizontal memory cells with enhanced high performance circuit density
US-2026020222-A1 · Jan 15, 2026 · US
3D isolation of a segmentated 3D nanosheet channel region
US-12513983-B2 · Dec 30, 2025 · US
Recent patents
Latest publications not already listed above.
Wafer overlay registration in hybrid bonding
US-2025391808-A1 · Dec 25, 2025 · US
3D isolation of a segmentated 3D nanosheet channel region
US-12507431-B2 · Dec 23, 2025 · US
3D advanced transistor architecture integrated with source/drain spider design
US-12507447-B2 · Dec 23, 2025 · US
3D hybrid memory using horizontally oriented conductive dielectric channel regions
US-12501602-B2 · Dec 16, 2025 · US
High performance 3D compact transistor architecture
US-12495604-B2 · Dec 9, 2025 · US
3D horizontal DRAM with in-situ bridge
US-12464703-B2 · Nov 4, 2025 · US
Three-dimensional plurality of N horizontal memory cells with enhanced high performance circuit density
US-12464704-B2 · Nov 4, 2025 · US
Vertical transistors and methods for forming the same
US-12457768-B2 · Oct 28, 2025 · US
In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
US-12455511-B2 · Oct 28, 2025 · US
Compact 3D design and connections with optimum 3D transistor stacking
US-12439641-B2 · Oct 7, 2025 · US
Contactless capacitive measurement tool with improved throughput and accuracy
US-12435964-B2 · Oct 7, 2025 · US
Reflecting non-planar surfaces integrated with laser scan for poseidon tool integration
US-2025297969-A1 · Sep 25, 2025 · US
Apparatus and method for determining the surface profile of a semiconductor substrate using a laser scanning technique
US-2025290745-A1 · Sep 18, 2025 · US
3D horizontal memory cell with sequential 3D vertical stacking
US-12408321-B2 · Sep 2, 2025 · US
Method of hybrid bonding using die distribution model
US-2025273619-A1 · Aug 28, 2025 · US
3D multiple location compressing bonded arm for advanced integration
US-12381118-B2 · Aug 5, 2025 · US
Method for selective exposure of wafer to corrective irradiation at a per-die level
US-2025244680-A1 · Jul 31, 2025 · US
2D material to integrate 3D horizontal nanosheets using a carrier nanosheet
US-12363956-B2 · Jul 15, 2025 · US
Methods for forming high performance three dimensionally stacked transistors based on dielectric nano sheets
US-12356706-B2 · Jul 8, 2025 · US
Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel
US-12349424-B2 · Jul 1, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 279 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 194 |
| H10D84/85 | 147 |
| H10D88/00 | 126 |
| H10D30/6735 | 119 |
| H10D88/01 | 114 |