3D advanced transistor architecture integrated with source/drain spider design

Patent metadata

Field	Value
Publication number	US-12507447-B2
Application number	US-202217672426-A
Country	US
Kind code	B2
Filing date	Feb 15, 2022
Priority date	Feb 15, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n junction with the source contact and a second p-n junction with the drain contact, and a gate structure comprising a gate dielectric and a gate contact contacting at least a portion of the channel between the first p-n junction and the second p-n junction. The source and drain contacts can comprise a doped semiconductor material and a channel having a first curved profile extending along the source contact and a second curved profile extending along the drain contact.

First claim

What is claimed is:

1 . A device comprising:
a first source contact; a first drain contact; a first carrier nanosheet including a first portion and a second portion; a first 2D material disposed on the first carrier nanosheet, the first 2D material forming a channel between the first source and first drain contacts and including a first portion, a second portion, and a third portion between the first and second portion, wherein the first and second portions respectively extend away from the third portion, wherein the first portion and the second portion of the first 2D material surround the first portion and the second portion of the first carrier nanosheet, respectively; and a first gate structure including a first gate dielectric and a first gate contact, the first gate structure surrounding at least the third portion of the first 2D material.

2 . The device of claim 1 , wherein at least one of the first source contact or the first drain contact include a doped semiconductor material.

3 . The device of claim 1 , wherein the first portion of the first 2D material includes a first curved profile extending along the first source contact and the second portion of the first 2D material includes a second curved profile extending along the first drain contact.

4 . The device of claim 1 , wherein the first carrier nanosheet includes silicon.

5 . The device of claim 1 , wherein:
the first portion of the first carrier nanosheet is doped to form a first p-n junction with the first source contact, and the second portion of the first carrier nanosheet is doped to form a second p-n junction with the first drain contact.

6 . The device of claim 1 , further comprising a first dielectric layer insulating the first gate contact from the first source contact and a second dielectric layer insulating the first gate contact from the first drain contact.

7 . The device of claim 5 , wherein at least one of the first p-n junction or the second p-n junction is formed to operate in a reverse bias.

8 . The device of claim 1 , further comprising:
a second source contact; a second drain contact; a second carrier nanosheet having a first portion and a second portion; a second 2D material forming a channel between the second source contact and the second drain contact and including a first portion, a second portion, and a third portion between the first and second portion, wherein the first and second portions respectively extend away from the third portion, wherein the first portion and the second portion of the second 2D material surround the first portion and the second portion of the second carrier nanosheet, respectively; and a second gate structure including a second gate dielectric and a second gate contact, the second gate structure surrounding at least the third portion of the second 2D material.

9 . The device of claim 1 , wherein the first portion of the first 2D material extends toward the first source contact and beyond the first portion of the first carrier nanosheet, and the second portion of the first 2D material extends toward the first drain contact and beyond the second portion of the first carrier nanosheet.

10 . The device of claim 1 , further comprising:
a first dielectric layer interposed between the first portion of the first carrier nanosheet and the first 2D material; and a second dielectric layer interposed between the second portion of the first carrier nanosheet and the first 2D material.

11 . The device of claim 10 , wherein the first dielectric layer includes a portion interposed between the third portion of the first 2D material and the first portion of the first carrier nanosheet, and the second dielectric layer includes a portion interposed between the third portion of the first 2D material and the second portion of the first carrier nanosheet.

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I
• Mukhopadhyay Partha

Classifications

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title