Three-dimensional plurality of N horizontal memory cells with enhanced high performance circuit density

Patent metadata

Field	Value
Publication number	US-12464704-B2
Application number	US-202217989348-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Mar 30, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor structure, comprising:
forming over a substrate a lower stack of a lower semiconductor layer and a lower doped semiconductor layer stacked over the lower semiconductor layer, the lower semiconductor layer and the lower doped semiconductor layer being parallel to a top surface of the substrate, the lower doped semiconductor layer including a lower doped first-type semiconductor layer and a lower doped second-type semiconductor layer within a transistor area and a capacitor area of the semiconductor structure, respectively, the lower semiconductor layer having one or more lower pillars; forming over the lower stack an upper stack of an upper semiconductor layer and an upper doped semiconductor layer stacked over the upper semiconductor layer, the upper semiconductor layer and the upper doped semiconductor layer being parallel to the top surface of the substrate, the upper doped semiconductor layer including an upper doped first-type semiconductor layer and an upper doped second-type semiconductor layer within the transistor area and the capacitor area of the semiconductor structure, respectively, the upper semiconductor layer having one or more upper pillars; forming over the substrate a lower transistor within the transistor area, the lower transistor including the lower doped first-type semiconductor layer as a lower channel thereof; forming over the lower transistor an upper transistor within the transistor area, the upper transistor including the upper doped first-type semiconductor layer as an upper channel thereof; forming over the substrate a lower capacitor within the capacitor area, the lower capacitor including the lower doped second-type semiconductor layer as a first lower plate thereof; and forming over the lower capacitor an upper capacitor within the capacitor area, the upper capacitor including the upper doped second-type semiconductor layer as a first upper plate thereof.

2 . The method of claim 1 , wherein the lower transistor has a lower gate region that wraps around the lower channel, and the upper transistor has an upper gate region that wraps around the upper channel.

3 . The method of claim 2 , wherein the upper gate region of the upper transistor is electrically connected to the lower gate region of the lower transistor.

4 . The method of claim 3 , wherein the lower transistor and the upper transistor are formed by:
removing the lower semiconductor layer of the lower stack and the upper semiconductor layer of the upper stack within the transistor area to uncover the lower doped first-type semiconductor layer of the lower doped semiconductor layer and the upper doped first-type semiconductor layer of the upper doped semiconductor layer; forming a first high-k dielectric layer to wrap around the lower doped first-type semiconductor layer of the lower doped semiconductor layer and the upper doped first-type semiconductor layer of the upper doped semiconductor layer that are uncovered as the lower gate region and the upper gate region, respectively; and forming a first metal layer to fill spaces that are generated after the lower semiconductor layer of the lower stack and the upper semiconductor layer of the upper stack are removed and the first high-k dielectric layer is formed to electrically connect the lower gate region to the upper gate region.

5 . The method of claim 1 , wherein the lower semiconductor layer contains a single crystal material, and the lower doped semiconductor layer is epitaxially formed on the lower semiconductor layer.

6 . The method of claim 1 , wherein the capacitor area is longer than the transistor area in a direction extending from the transistor area to the capacitor area.

7 . The method of claim 1 , wherein the lower capacitor further has a lower charge storage layer that wraps around the first lower plate, and the upper capacitor further has an upper charge storage layer that wraps around the first upper plate.

8 . The method of claim 7 , wherein the lower capacitor further has a second lower plate that wraps around the lower charge storage layer, and the upper capacitor further has a second upper plate that wraps around the upper charge storage layer.

9 . The method of claim 8 , wherein the second upper plate of the upper capacitor is electrically connected to the second lower plate of the lower capacitor.

10 . The method of claim 9 , wherein the lower capacitor and the upper capacitor are formed by:
removing the lower semiconductor layer of the lower stack and the upper semiconductor layer of the upper stack within the capacitor area to uncover the lower doped second-type semiconductor layer of the lower doped semiconductor layer and the upper doped second-type semiconductor layer of the upper doped semiconductor layer as the first lower plate and the first upper plate, respectively; forming a second high-k dielectric layer to wrap around the lower doped second-type semiconductor layer of the lower doped semiconductor layer and the upper doped second-type semiconductor layer of the upper doped semiconductor layer that are uncovered as the lower charge storage layer and the upper charge storage layer, respectively; and forming a second metal layer to fill spaces that are generated after the lower semiconductor layer of the lower stack and the upper semiconductor layer of the upper stack are removed and the second high-k dielectric layer is formed as the second lower plate and the second upper plate.

11 . The method of claim 1 , wherein the lower transistor is insulated from the substrate.

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I
• Mukhopadhyay Partha

Classifications

• H10B12/05

  Making the transistor · CPC title

• H10B12/03 Primary

  Making the capacitor or connections thereto · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title