Contactless capacitive measurement tool with improved throughput and accuracy

US12435964B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12435964-B2
Application numberUS-202318511086-A
CountryUS
Kind codeB2
Filing dateNov 16, 2023
Priority dateNov 16, 2023
Publication dateOct 7, 2025
Grant dateOct 7, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods are provided herein for determining the planarity of a semiconductor wafer. The systems and methods described herein utilize a capacitive measurement tool to detect and characterize the bow of a semiconductor wafer. The capacitive measurement tool disclosed herein utilizes a non-contact, capacitive sensor unit to measure wafer bow. Unlike conventional capacitive sensing techniques used to measure wafer bow, the capacitive sensor unit disclosed herein uses a plurality of electrodes for simultaneously obtaining a plurality of capacitance measurements from the wafer at various locations on the wafer surface. By including a plurality of electrodes within the capacitive sensor unit, the techniques described herein increase the amount of data collected across the wafer surface at any given time to improve the throughput and measurement accuracy of the capacitive measurement tool.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a wafer mount configured to support a semiconductor wafer; a capacitive sensor unit including: a sensor housing having a first surface, the first surface facing a surface of the semiconductor wafer when the capacitive sensor unit is in close proximity to the semiconductor wafer; and a plurality of electrodes provided on the first surface of the sensor housing and laterally spaced from one another, wherein each electrode works in conjunction with a corresponding opposing area on the surface of the semiconductor wafer to form a capacitor with: (a) the electrode forming a top plate of the capacitor, and (b) the corresponding opposing area on the surface of the semiconductor wafer forming a bottom plate of the capacitor; and a controller configured to: (a) obtain a plurality of capacitance values from the plurality of electrodes by measuring a capacitance between each electrode and the corresponding opposing area on the surface of the semiconductor wafer, (b) calculate a distance between each electrode and the corresponding opposing area of the surface of the semiconductor wafer based on the capacitance value measured at the electrode, and (c) determine a bow of the semiconductor wafer based on the calculated distances. 2. The system of claim 1 , wherein the capacitive sensor unit is a disc-shaped capacitive sensor unit, and wherein the first surface of the sensor housing has a circular surface area substantially equal to a circular surface area of the semiconductor wafer. 3. The system of claim 2 , wherein the plurality of electrodes comprises 10 to 100 electrodes, which are laterally spaced across the first surface of the sensor housing of the disc-shaped capacitive sensor unit in a two-dimensional (2D) electrode array. 4. The system of claim 3 , wherein the controller uses the 2D electrode array to simultaneously obtain the plurality of capacitance values from the plurality of electrodes, while the semiconductor wafer is held stationary by the wafer mount and the disc-shaped capacitive sensor unit is held stationary a fixed distance away from the surface of the semiconductor wafer. 5. The system of claim 1 , wherein the capacitive sensor unit is a bar-shaped capacitive sensor unit, and wherein a length of the sensor housing is substantially equal to a diameter of the semiconductor wafer. 6. The system of claim 5 , wherein the plurality of electrodes comprises 10 to 100 electrodes, which are laterally spaced across the first surface of the sensor housing of the bar-shaped capacitive sensor unit in a linear electrode array. 7. The system of claim 6 , wherein the controller uses the linear electrode array to simultaneously obtain the plurality of capacitance values from the plurality of electrodes, while the bar-shaped capacitive sensor unit is positioned a fixed distance away from a surface of the semiconductor wafer and either: (a) the bar-shaped capacitive sensor unit is scanned in a linear direction across the surface of the semiconductor wafer, while the semiconductor wafer is held stationary by the wafer mount, or (b) the bar-shaped capacitive sensor unit is held stationary, while the semiconductor wafer is scanned in a linear direction by the wafer mount. 8. The system of claim 1 , wherein the capacitive sensor unit is a bar-shaped capacitive sensor unit, and wherein a length of the sensor housing is substantially equal to a radius of the semiconductor wafer. 9. The system of claim 8 , wherein the plurality of electrodes comprises 10 to 50 electrodes, which are laterally spaced across the first surface of the sensor housing of the bar-shaped capacitive sensor unit in a radial electrode array. 10. The system of claim 9 , wherein the controller uses the radial electrode array to simultaneously obtain the plurality of capacitance values from the plurality of electrodes, while the bar-shaped capacitive sensor unit is positioned a fixed distance away from a surface of the semiconductor wafer and either: (a) the bar-shaped capacitive sensor unit is rotated across the surface of the semiconductor wafer, while the semiconductor wafer is held stationary by the wafer mount, or (b) the semiconductor wafer is rotated by the wafer mount, while the bar-shaped capacitive sensor unit is held stationary. 11. The system of claim 1 , wherein the semiconductor wafer and the capacitive sensor unit are supported in a horizontal orientation, or a vertical orientation, while the plurality of capacitance values are obtained. 12. The system of claim 1 , wherein the system is a wafer processing system, and wherein the wafer mount and the capacitive sensor unit are included within a metrology tool, which is provided within the wafer processing system for measuring a wafer bow of at least one semiconductor wafer processed by the wafer processing system. 13. A metrology tool for measuring wafer bow, the metrology tool comprising: a wafer mount configured to support a semiconductor wafer; a bar-shaped capacitive sensor unit including: a sensor housing having a first surface, the first surface facing a surface of the semiconductor wafer when the bar-shaped capacitive sensor unit is in close proximity to the semiconductor wafer; and a plurality of electrodes provided on the first surface of the sensor housing and arranged in a line along a length of the sensor housing, wherein each electrode works in conjunction with a corresponding opposing area on the surface of the semiconductor wafer to form a capacitor with: (a) the electrode forming a top plate of the capacitor, and (b) the corresponding opposing area on the surface of the semiconductor wafer forming a bottom plate of the capacitor; a movement device configured to move at least one of the wafer mount and the bar-shaped capacitive sensor unit relative to each other; and a controller configured to: (a) obtain a plurality of capacitance values from the plurality of electrodes by measuring a capacitance between each electrode and the corresponding opposing area on the surface of the semiconductor wafer, (b) calculate a distance between each electrode and the corresponding opposing area of the surface of the semiconductor wafer based on the capacitance value measured at the electrode, and (c) determine a bow of the semiconductor wafer based on the calculated distances. 14. The metrology tool of claim 13 , wherein a length of the sensor housing is substantially equal to a diameter of the semiconductor wafer. 15. The metrology tool of claim 14 , wherein the plurality of electrodes comprises 10 to 100 electrodes, which are laterally spaced across the first surface of the sensor housing of the bar-shaped capacitive sensor unit in a linear electrode array. 16. The metrology tool of claim 15 , wherein the controller uses the linear electrode array to simultaneously obtain the plurality of capacitance values from the plurality of electrodes, while the bar-shaped capacitive sensor unit is positioned a fixed distance away from a surface of the semiconductor wafer and either: (a) the bar-shaped capacitive sensor unit is scanned in a linear direction across the surface of the semiconductor wafer by the movement device, while the semiconductor wafer is held stationary by the wafer mount, or (b) the bar-shaped capacitive sensor unit is held stationary, while the semiconductor wafer supported by the wafer mount is scanned in a linear direction by the movement device. 17. The metrology tool of claim 13 , wherein a length of the sensor housing is substantially equal to a radius of the semiconductor wafer. 18. T

Assignees

Inventors

Classifications

  • Monitoring of warpages, curvatures, damages, defects or the like · CPC title

  • Position monitoring, e.g. misposition detection or presence detection · CPC title

  • G01B7/345Primary

    for measuring evenness · CPC title

  • Measuring capacitance (capacitive sensors G01D5/24) · CPC title

  • by varying capacitance · CPC title

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What does patent US12435964B2 cover?
Systems and methods are provided herein for determining the planarity of a semiconductor wafer. The systems and methods described herein utilize a capacitive measurement tool to detect and characterize the bow of a semiconductor wafer. The capacitive measurement tool disclosed herein utilizes a non-contact, capacitive sensor unit to measure wafer bow. Unlike conventional capacitive sensing tech…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification G01B7/345. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).