3D hybrid memory using horizontally oriented conductive dielectric channel regions

Patent metadata

Field	Value
Publication number	US-12501602-B2
Application number	US-202217866154-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Jul 16, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a semiconductor device includes a first transistor comprising a first channel region. The first channel region includes one or more first nanostructures formed of a semiconductor material. The semiconductor device includes a second transistor disposed vertically with respect to the first transistor and comprising a second channel region. The second channel region includes one or more second nanostructures formed of a conductive oxide material.

First claim

What is claimed is:

1 . A structure, comprising:
a dielectric layer directly contacting a semiconductor substrate; a first transistor disposed on the dielectric layer and comprising a first channel region, wherein the first channel region includes one or more first nanostructures formed of a semiconductor material, and wherein a gate electrode of the first transistor is interposed between the dielectric layer and a gate dielectric layer; and a second transistor disposed vertically with respect to the first transistor and comprising a second channel region, wherein the second channel region includes one or more second nanostructures formed of a conductive oxide material.

2 . The structure of claim 1 , wherein the oxide material is a nanosheet of indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), or tin oxide (SnO).

3 . The structure of claim 1 , wherein the gate electrode of the first transistor is coupled to a drain of the second transistor.

4 . The structure of claim 3 , wherein the second transistor is stacked over the first transistor.

5 . The structure of claim 1 , wherein the second transistor is stacked over the first transistor, the structure further comprising a conductive via coupling a gate of the first transistor to a drain of the second transistor.

6 . The structure of claim 1 , wherein the first and second channel regions each comprise at least two parallel nanosheets.

7 . The structure of claim 1 , wherein the first and second transistor are connected as a DRAM cell, one of the first or second transistors being a select transistor and the other of the first or second transistor being a storage node.

8 . A method comprising:
providing a stack of layers comprising:
a layer of a first sacrificial material;
a first layer of a second sacrificial material;
at least one semiconductor channel layer on the first layer of the second sacrificial material with a second or additional layer of the second sacrificial material provided over each semiconductor channel layer;
an insulation layer;
the stack of layers having alternating layers of an oxide channel layer and a third sacrificial material; and
a lowermost layer and an uppermost layer in the stack of layers comprising the third sacrificial material;
patterning the layers to form a plurality of transistor core stacks isolated from each other by an insulating layer; etching first openings on first opposing sides of each transistor core stack to access the first sacrificial material; removing the first sacrificial material and replacing the removed material with an insulating material, etching second openings on second opposing sides of each transistor core stack; partially etching the layers of second sacrificial material and third sacrificial material; selectively forming a dielectric material on the layers of second and third sacrificial materials, forming first source/drain regions adjacent the at least one semiconductor channel layer and second source/drain regions adjacent the at least one oxide channel layer; removing the second and third sacrificial materials through the first openings; forming high-k gate dielectric materials selectively around the at least one semiconductor channel layer and the at least one oxide channel layer; forming a first gate surrounding the at least one semiconductor channel layer; and forming a second gate surrounding the at least one oxide channel layer.

9 . The method of claim 8 , further comprising forming a conductive via coupling one of the second source/drain regions to the first gate.

10 . A structure comprising:
an insulating layer directly contacting a semiconductor substrate; at least two first transistors comprising a first channel region, wherein the first channel region includes one or more first nanostructures formed of a semiconductor material, a gate electrode of one of the at least two first transistors is disposed between the insulating layer and a gate dielectric layer; and at least one second transistor disposed vertically with respect to the first transistor and comprising a second channel region, wherein the second channel region includes one or more second nanostructures formed of a conductive oxide material.

11 . The structure of claim 10 , further comprising at least two transistors having a plurality of first channel regions comprising the semiconductor material.

12 . The structure of claim 11 , wherein at least one of the at least two transistors has at least one of the plurality of first channel regions comprising the semiconductor material and is an n-type device and at least one other of the at least two transistors has at least one of the plurality of first channel regions comprising the semiconductor material and is a p-type device.

13 . The structure of claim 11 , further comprising at least two second transistors having second channel regions comprising an oxide material.

14 . The structure of claim 13 , wherein at least one of the at least two transistors having the plurality of first channel regions comprising the semiconductor material being an n-type device, and at least one of the at least two transistors having the plurality of first channel regions comprising the semiconductor material being a p-type device.

15 . The structure of claim 10 , wherein the oxide material is a nanosheet of indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), or tin oxide (SnO).

16 . A structure comprising:
a semiconductor substrate; a dielectric layer disposed on the semiconductor substrate; a first stack of transistors with at least one p-type semiconductor nanostructure and one n-type semiconductor nanostructure coupled to the at least one p-type semiconductor nanostructure as a complementary transistor pair, a gate electrode of a bottommost transistor in the first stack interposed between the dielectric layer and a gate dielectric layer; at least one first transistor having at least one first channel region comprising a semiconductor material or an oxide material; and at least one second transistor having at least one second channel region comprising an oxide material.

17 . The structure of claim 16 , wherein the oxide material is a nanosheet of indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), or tin oxide (SnO).

18 . The structure of claim 16 , wherein the first and second transistor are connected as a DRAM cell, one of the first or second transistors being a select transistor and the other of the first or second transistor being a storage node.

19 . The structure of claim 16 , wherein the first stack of transistors further comprises:
a third transistor having at least one third channel region comprising the semiconductor material; and a fourth transistor having at least one fourth channel region comprising the oxide material or the semiconductor material.

20 . The structure of claim 16 , further comprising a second stack of transistors disposed laterally from the first stack of transistors, the second stack of transistors comprising:
at least one p-type semiconductor nanostructure and one n-type semiconductor nanostructure coupled to the at least one p-type semiconductor device as a complementary transistor pair; at least one third transistor having at least one third channel region comprising the semiconductor material or the oxide material; and at least one fourth transistor having at l

Assignees

• Tokyo Electron Ltd

Inventors

• Gardner Mark I
• Fulford H Jim
• Mukhopadhyay Partha

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title