High performance 3D compact transistor architecture

Patent metadata

Field	Value
Publication number	US-12495604-B2
Application number	US-202217945888-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Sep 15, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another, wherein different materials are simultaneously epitaxial-grown for the first semiconductor channels and the second semiconductor channels, can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

First claim

What is claimed is:

1 . A method, comprising:
providing a plurality of first semiconductor films and a plurality of second semiconductor films alternately stacked on top of one another and a plurality of third semiconductor films and a plurality of fourth semiconductor films alternately stacked on top of one another, wherein the first semiconductor films and fourth semiconductor films contain a first semiconductor material, the second semiconductor films and third semiconductor films contain a second semiconductor material, and the first and second semiconductor films each have a first sidewall in contact with a dielectric structure and the third and fourth semiconductor films each have a first sidewall in contact with the dielectric structure; removing the second semiconductor films; forming a first gate structure around at least a top surface, a bottom surface, and a second sidewall of each of the first semiconductor films opposite to its respective first sidewall; removing the fourth semiconductor films; and forming a second gate structure around at least a top surface, a bottom surface, and a second sidewall of each of the third semiconductor films opposite to its respective first sidewall, wherein each of the first semiconductor films is laterally aligned with a corresponding one of the third semiconductor films, and each of the second semiconductor films is laterally aligned with a corresponding one of the fourth semiconductor films.

2 . The method of claim 1 , further comprising:
forming, over a first portion of a substrate, a first semiconductor layer containing the first semiconductor material; forming, over the first portion of the substrate and further over a second portion of the substrate, a second semiconductor layer containing the second semiconductor material; forming, over the first and second portions of the substrate, a third semiconductor layer containing the first semiconductor material; forming, over the first and second portions of the substrate, a fourth semiconductor layer containing the second semiconductor material; and forming, over the first and second portions of the substrate, a fifth semiconductor layer containing the first semiconductor material.

3 . The method of claim 2 , further comprising:
patterning the first to fifth semiconductor layers to form a first stack and a second stack disposed in the first portion and in the second portion, respectively; wherein the first stack includes the alternately stacked third semiconductor films and fourth semiconductor films, and the second stack includes the alternately stacked first semiconductor films and second semiconductor films.

4 . The method of claim 3 , wherein the second stack further includes a fifth semiconductor film disposed on a topmost one of the first semiconductor films, and wherein the semiconductor film contains a third semiconductor material similar to the second semiconductor material.

5 . The method of claim 1 , wherein the first gate structure includes a first gate electrode and the second gate structure includes a second gate electrode, and wherein the first gate electrode and second gate electrode have opposite conductive types.

6 . The method of claim 1 , wherein the first semiconductor material comprises silicon germanium, and the second semiconductor material comprises silicon.

7 . The method of claim 1 , wherein the first semiconductor material is configured for a first transistor with a first conductive type, and the second semiconductor material is configured for a second transistor with a second conductive type.

8 . The method of claim 1 , further comprising:
forming a pair of first source/drain regions in contact with opposite third and fourth sidewalls of each of the first semiconductor films; and forming a pair of second source/drain regions in contact with opposite third and fourth sidewalls of each of the third semiconductor films.

9 . The method of claim 1 , further comprising:
prior to forming the pair of first source/drain regions, replacing at least end portions of the first gate structure that are interposed between neighboring ones of the first semiconductor films with a plurality of first dielectric spacers, respectively; and prior to forming the pair of second source/drain regions, replacing at least end portions of the second gate structure that are interposed between neighboring ones of the third semiconductor films with a plurality of second dielectric spacers, respectively.

10 . A method, comprising:
forming, over a first portion of a substrate, a first stack comprising a plurality of first semiconductor films and a plurality of second semiconductor films alternately stacked on top of one another; concurrently with forming the first stack, forming, over a second portion of the substrate, a second stack comprising a plurality of third semiconductor films and a plurality of fourth semiconductor films alternately stacked on top of one another, wherein the first semiconductor films and fourth semiconductor films contain a first semiconductor material, and the second semiconductor films and third semiconductor films contain a second semiconductor material; forming a dielectric structure interposed between the first stack and the second stack; removing the second semiconductor films; forming a first gate structure around at least a top surface, a bottom surface, and a first sidewall of each of the first semiconductor films opposite to its respective first sidewall in contact with the dielectric structure; removing the fourth semiconductor films; and forming a second gate structure around at least a top surface, a bottom surface, and a second sidewall of each of the third semiconductor films opposite to its respective first sidewall in contact with the dielectric structure, wherein each of the first semiconductor films is laterally aligned with a corresponding one of the third semiconductor films, and each of the second semiconductor films is laterally aligned with a corresponding one of the fourth semiconductor films.

11 . The method of claim 10 , wherein the first gate structure includes a first gate electrode and the second gate structure includes a second gate electrode, and wherein the first gate electrode and second gate electrode have opposite conductive types.

12 . The method of claim 10 , wherein the first semiconductor material comprises silicon germanium, and the second semiconductor material comprises silicon.

13 . The method of claim 10 , wherein the first semiconductor material is configured for a first transistor with a first conductive type, and the second semiconductor material is configured for a second transistor with a second conductive type.

14 . The method of claim 10 , further comprising:
forming a pair of first source/drain regions in contact with opposite third and fourth sidewalls of each of the first semiconductor films; and forming a pair of second source/drain regions in contact with opposite third and fourth sidewalls of each of the third semiconductor films.

15 . The method of claim 14 , further comprising:
prior to forming the pair of first source/drain regions, replacing at least end portions of the first gate structure that are interposed between neighboring ones of the first semiconductor films with a plurality of first dielectric spacers, respectively; and prior to forming the pair of second source/drain regions, replacing at least end portions of the second gate structure that are interposed between neighboring ones of the third semiconductor films with a plurality of second dielectric spacers, respecti

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title