Method of making 3D memory stacking formation with high circuit density

Patent metadata

Field	Value
Publication number	US-12598734-B2
Application number	US-202218073118-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Mar 16, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein at least one DRAM cell unit comprises a transistor and a capacitor, wherein the capacitor comprises: a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer, wherein the capacitor is elongated in a horizontal direction parallel to the working surface of the substrate, and the second metal layer has a first end and a second end in the horizontal direction, wherein the transistor comprises: a channel structure, and a gate structure disposed all around the channel structure, wherein the first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor, the capacitor dielectric layer is at least partially at a higher level in the vertical direction than the channel structure, the second metal layer is at least partially at a higher level in the vertical direction than the channel structure, the first metal layer is coplanar with the channel structure, and the drain region and the source region of the first metal layer are in direct contact with the channel structure.

2 . The semiconductor device of claim 1 , wherein:
the channel structure comprises a semiconducting oxide positioned between the drain region and the source region.

3 . The semiconductor device of claim 2 , wherein:
the channel structure further comprises a two-dimensional (2D) semiconductor material disposed all around the semiconducting oxide.

4 . The semiconductor device of claim 3 , wherein:
the 2D semiconductor material extends beyond the semiconducting oxide in the horizontal direction and is disposed all around the drain region and the source region.

5 . The semiconductor device of claim 1 , further comprising:
a common ground structure configured to electrically connect to a plurality of second metal layers of a plurality of DRAM cell units of the stack of DRAM cell units on respective second ends.

6 . A semiconductor device, comprising:
a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein at least one DRAM cell unit comprises a transistor and a capacitor, wherein the capacitor comprises: a first metal laver, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer, wherein the capacitor is elongated in a horizontal direction parallel to the working surface of the substrate, and the second metal layer has a first end and a second end in the horizontal direction, wherein the transistor comprises: a channel structure, and a gate structure disposed all around the channel structure, wherein the first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor, the capacitor dielectric layer is at least partially at a higher level in the vertical direction than the channel structure, the second metal layer is at least partially at a higher level in the vertical direction than the channel structure, and a capacitor metal portion of the first metal layer, which is in direct contact with the capacitor dielectric layer, is wider than the drain region and the source region in another horizontal direction.

7 . The semiconductor device of claim 1 , wherein:
the channel structure is configured to have a current flow path in the horizontal direction.

8 . The semiconductor device of claim 1 , further comprising:
a dielectric material positioned between the gate structure and the capacitor dielectric layer.

9 . The semiconductor device of claim 8 , wherein the capacitor dielectric layer comprises:
a horizontal portion positioned between the second metal layer and the first metal layer; and a vertical portion positioned between the second metal layer and the dielectric material.

10 . A method of manufacturing a semiconductor device, the method comprising:
forming a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein at least one DRAM cell unit comprises a transistor and a capacitor, and the forming the stack of DRAM cell units comprises forming the transistor and forming the capacitor, wherein the forming the capacitor comprises: forming a first metal laver, forming a capacitor dielectric layer positioned on the first metal layer, and forming a second metal layer positioned on the capacitor dielectric layer, wherein the capacitor is elongated in a horizontal direction parallel to the working surface of the substrate, and the second metal layer has a first end and a second end in the horizontal direction, wherein the forming the transistor comprises: forming a channel structure, and forming a gate structure disposed all around the channel structure, wherein the first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor, the capacitor dielectric layer is at least partially at a higher level in the vertical direction than the channel structure, the second metal layer is at least partially at a higher level in the vertical direction than the channel structure, the first metal layer is coplanar with the channel structure, and the drain region and the source region of the first metal layer are in direct contact with the channel structure.

11 . The method of claim 10 , wherein the forming the channel structure comprises:
forming a semiconducting oxide between the drain region and the source region.

12 . The method of claim 11 , further comprising:
forming a two-dimensional (2D) semiconductor material all around the semiconducting oxide.

13 . The method of claim 12 , wherein:
the 2D semiconductor material extends beyond the semiconducting oxide in the horizontal direction and is disposed all around the drain region and the source region.

14 . The method of claim 10 , further comprising:
forming a common ground structure configured to electrically connect to a plurality of second metal layers of a plurality of DRAM cell units of the stack of DRAM cell units on respective second ends.

15 . The method of claim 10 , further comprising:
forming the channel structure in the first metal layer; and forming a sacrificial material over and below the channel structure.

16 . The method of claim 15 , further comprising:
uncovering the transistor from two opposing sides; removing the sacrificial material; and forming the gate structure all around the channel structure.

17 . The method of claim 16 , wherein:
the drain region and the source region are uncovered as a result of the removing the sacrificial material.

18 . The method of claim 10 , wherein:
a capacitor metal portion of the first metal layer, which is in direct contact with the capacitor dielectric layer, is wider than the drain region and the source region in another horizontal direction.

19 . The method of claim 18 , wherein:
the another horizontal direction is perpendicular to the horizontal direction.

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I
• Mukhopadhyay Partha

Classifications

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10B12/05

  Making the transistor · CPC title