Transistor stacking by wafer bonding

Patent metadata

Field	Value
Publication number	US-12543369-B2
Application number	US-202217884192-A
Country	US
Kind code	B2
Filing date	Aug 9, 2022
Priority date	Dec 29, 2021
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A method of fabricating a semiconductor device includes receiving a first wafer including a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer. The first SOI stack includes a first semiconductor. A second wafer is received that includes a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer. The second SOI stack includes a second semiconductor. The front side of the first wafer is bonded to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer. The second substrate is removed. A stack of transistor devices is formed with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
receiving a first wafer comprising a first substrate on a backside of the first wafer, and a first semiconductor-on-insulator (SOI) stack on a front side of the first wafer, the first SOI stack comprising a first insulator, one layer of a second insulator over the first insulator, and a first semiconductor over the one layer of the second insulator, the first wafer further comprising another layer of the second insulator over the first semiconductor, the first insulator and the second insulator configured to be etch-selective to each other; receiving a second wafer comprising a second substrate on a backside of the second wafer, and a second SOI stack on a front side of the second wafer, the second SOI stack comprising a third insulator, one layer of a fourth insulator over the third insulator, and a second semiconductor over the one layer of the fourth insulator, the second wafer further comprising another layer of the fourth insulator over the second semiconductor, the third insulator and the fourth insulator configured to be etch-selective to each other; bonding the front side of the first wafer to the front side of the second wafer, via at least one dielectric bonding material, to form a bonded wafer; removing the second substrate from the bonded wafer; and forming a stack of transistor devices with the first semiconductor used as a first channel for a first transistor and the second semiconductor used as a second channel for a second transistor.

2 . The method of claim 1 , wherein the bonding the front side of the first wafer to the front side of the second wafer comprises:
bonding a first dielectric layer, which is on the front side of the first wafer, to a second dielectric layer, which is on the front side of the second wafer.

3 . The method of claim 2 , wherein:
the first dielectric layer and the second dielectric layer comprise a same dielectric bonding material, and the bonding the first dielectric layer to the second dielectric layer comprises performing fusion bonding.

4 . The method of claim 1 , further comprising patterning the bonded wafer to form at least one layer stack over the first substrate, wherein the at least one layer stack comprises:
the first semiconductor over the first substrate; the at least one dielectric bonding material over the first semiconductor; and the second semiconductor over the at least one dielectric bonding material.

5 . The method of claim 4 , further comprising:
uncovering opposing sidewalls of the at least one layer stack; and forming source/drain (S/D) regions on opposing sides of the first semiconductor and opposing sides of the second semiconductor.

6 . The method of claim 4 , further comprising:
uncovering opposing sidewalls of the at least one layer stack; uncovering top and bottom surfaces of the first semiconductor and top and bottom surfaces of the second semiconductor; and forming gate structures around the first semiconductor and the second semiconductor.

7 . The method of claim 4 , further comprising:
uncovering opposing sidewalls of the at least one layer stack; and replacing end portions of insulator layers with dielectric spacers, the insulator layers respectively being in direct contact with the first semiconductor and the second semiconductor.

8 . The method of claim 1 , wherein:
the receiving the first wafer comprises forming the first SOI stack over the first substrate and forming the another layer of the second insulator over the first SOI stack, the receiving the second wafer comprises forming the second SOI stack over the second substrate and forming the another layer of the fourth insulator over the second SOI stack, and the one layer of the second insulator is in direct contact with the first insulator.

9 . The method of claim 1 , wherein the bonding the front side of the first wafer to the front side of the second wafer, via the at least one dielectric bonding material, to form the bonded wafer comprises:
bonding a first dielectric layer, which is over the another layer of the second insulator of the first wafer, directly to a second dielectric layer, which is over the another layer of the fourth insulator of the second wafer, wherein the first dielectric layer and the second dielectric layer comprise a same dielectric material, and there is no bonding defect between the first dielectric layer and the second dielectric layer.

10 . The method of claim 1 , wherein:
the first transistor comprises a first channel that is single crystalline, and the second transistor comprises a second channel that is single crystalline.

11 . The method of claim 10 , wherein:
the first semiconductor over the one layer of the second insulator is single crystal silicon, and the second semiconductor over the one layer of the fourth insulator is single crystal germanium.

12 . A semiconductor device, comprising:
a substrate; a stack of transistors over the substrate, the stack of transistors comprising a first transistor and a second transistor stacked over the first transistor, wherein the first transistor comprises a first channel surrounded by a first gate structure, and first S/D regions on opposing ends of the first channel, and the second transistor comprises a second channel surrounded by the second gate structure, and second S/D regions on opposing ends of the second channel; an isolation structure positioned between the first transistor and the second transistor, the isolation structure comprising a first dielectric layer, which is in direct contact with the first gate structure of the first transistor, and a second dielectric layer, which is in direct contact with the second gate structure of the second transistor; and a common vertical conductive structure that is in direct contact with one of the first S/D regions and one of the second S/D regions, wherein the first dielectric layer is directly bonded to the second dielectric layer.

13 . The semiconductor device of claim 12 , wherein:
the first dielectric layer and the second dielectric layer comprise a same dielectric material, there is no bonding defect between the first dielectric layer and the second dielectric layer, and the first dielectric layer is bonded seamlessly to the second dielectric layer.

14 . The semiconductor device of claim 12 , wherein:
the first dielectric layer is bonded to the second dielectric layer with one or more bonding defects at a bonding interface between the first dielectric layer and the second dielectric layer, and the one or more bonding defects include at least one selected from the group consisting of a trapped particle and a crack.

15 . The semiconductor device of claim 12 , wherein:
at least one channel of the stack of transistors comprises an elemental semiconductor or a compound semiconductor.

16 . The semiconductor device of claim 12 , wherein:
the first transistor comprises a first channel that is single crystalline, and the second transistor comprises a second channel that is single crystalline.

17 . The semiconductor device of claim 12 , wherein:
the first transistor includes a single first channel without additional channels, and the second transistor includes a single second channel without additional channels.

18 . The semiconductor device of claim 12 , wherein when viewed from a vertical direction substantially perpendicular to a working surface of the substrate:
the isolation structure completely overl

Assignees

• Tokyo Electron Ltd

Inventors

• Gardner Mark I
• Fulford H Jim

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H01L21/76251

  Electricity · mapped topic

• H10D86/01 Primary

  Manufacture or treatment · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914 Primary

  using bonding · CPC title