Compact 3D design and connections with optimum 3D transistor stacking

Patent metadata

Field	Value
Publication number	US-12439641-B2
Application number	US-202217714716-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Nov 19, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first transistor comprising a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure; and
a second transistor comprising a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure,
wherein the second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

2. A semiconductor device, comprising:
a first transistor comprising a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure; and
a second transistor comprising a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure,
wherein the second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate, and the ends of the first channel structure are offset in the horizontal direction from the ends of the second channel structure.

3. The semiconductor device of claim 2 , wherein:
the ends of the first channel structure each extend outwardly in the horizontal direction from a respective end of the second channel structure.

4. A semiconductor device, comprising:
a first transistor comprising a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure;
a second transistor comprising a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure, wherein the second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate;
first vertical contact structures connected to the first S/D regions, wherein the first vertical contact structures bypass the second transistor; and
second vertical contact structures connected to the second S/D regions.

5. The semiconductor device of claim 1 , wherein:
the first channel structure and the second channel structure comprise different chemical compositions.

6. The semiconductor device of claim 1 , wherein:
the first transistor comprises a plurality of first channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the first S/D regions are connected to the plurality of first channel structures, and
the first gate structure is disposed all around the plurality of first channel structures and separates the plurality of first channel structures from each other.

7. The semiconductor device of claim 1 , wherein:
the second transistor comprises a plurality of second channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the second S/D regions are connected to the plurality of second channel structures, and
the second gate structure is disposed all around the plurality of second channel structures and separates the plurality of second channel structures from each other.

8. The semiconductor device of claim 1 , further comprising:
first inner spacers positioned between the first gate structure and the first S/D regions; and
second inner spacers positioned between the second gate structure and the second S/D regions.

9. The semiconductor device of claim 2 , wherein:
the first channel structure and the second channel structure comprise different chemical compositions.

10. The semiconductor device of claim 2 , wherein:
the first transistor comprises a plurality of first channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the first S/D regions are connected to the plurality of first channel structures, and
the first gate structure is disposed all around the plurality of first channel structures and separates the plurality of first channel structures from each other.

11. The semiconductor device of claim 2 , wherein:
the second transistor comprises a plurality of second channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the second S/D regions are connected to the plurality of second channel structures, and
the second gate structure is disposed all around the plurality of second channel structures and separates the plurality of second channel structures from each other.

12. The semiconductor device of claim 2 , further comprising:
first inner spacers positioned between the first gate structure and the first S/D regions; and
second inner spacers positioned between the second gate structure and the second S/D regions.

13. The semiconductor device of claim 2 , further comprising:
first vertical contact structures connected to the first S/D regions, wherein the first vertical contact structures bypass the second transistor; and
second vertical contact structures connected to the second S/D regions.

14. The semiconductor device of claim 3 , further comprising:
first vertical contact structures connected to the first S/D regions, wherein the first vertical contact structures bypass the second transistor; and
second vertical contact structures connected to the second S/D regions.

15. The semiconductor device of claim 4 , wherein:
the first channel structure and the second channel structure comprise different chemical compositions.

16. The semiconductor device of claim 4 , wherein:
the first transistor comprises a plurality of first channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the first S/D regions are connected to the plurality of first channel structures, and
the first gate structure is disposed all around the plurality of first channel structures and separates the plurality of first channel structures from each other.

17. The semiconductor device of claim 4 , wherein:
the second transistor comprises a plurality of second channel structures stacked in a vertical direction substantially perpendicular to the working surface of the substrate,
the second S/D regions are connected to the plurality of second channel structures, and
the second gate structure is disposed all around the plurality of second channel structures and separates the plurality of second channel structures from each other.

18. The semiconductor device of claim 4 , further comprising:
first inner spacers positioned between the first gate structure and the first S/D regions; and
second inner spacers positioned between the second gate structure and the second S/D regions.

19. The semiconductor device of claim 5 , wherein:
the first transistor comprises a plurality of first channel structures stacked in a vertical dir

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I
• Mukhopadhyay Partha

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title