3D high density self-aligned nanosheet device formation with efficient layout and design

Patent metadata

Field	Value
Publication number	US-12538520-B2
Application number	US-202217714678-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Aug 20, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

First claim

What is claimed is:

1 . A method of microfabrication, the method comprising:
forming an initial stack of semiconductor layers by epitaxial growth over a substrate, the initial stack of semiconductor layers comprising channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate, the channel structures comprising a first channel structure and a second channel structure positioned above the first channel structure, wherein the initial stack of semiconductor layers is surrounded by a sidewall structure; removing first portions of the sidewall structure to uncover first sides of the initial stack; forming source/drain (S/D) regions on uncovered side surfaces of the channel structures from the first sides of the initial stack; removing second portions of the sidewall structure to uncover second sides of the initial stack; and replacing the sacrificial gate layers with gate structures from the second sides of the initial stack.

2 . The method of claim 1 , further comprising:
forming indentations by removing end portions of the sacrificial gate layers from the first sides of the initial stack; and forming inner spacers in the indentations.

3 . The method of claim 1 , wherein the replacing the sacrificial gate layers with the gate structures comprises:
forming the gate structures all around respective channel structures.

4 . The method of claim 1 , wherein the replacing the sacrificial gate layers with the gate structures comprises:
forming at least one gate dielectric of the gate structures over uncovered portions of the channel structures; and forming at least one work function metal (WFM) of the gate structures over the at least one gate dielectric.

5 . The method of claim 4 , wherein the forming the at least one gate dielectric of the gate structures comprises:
selectively depositing the at least one dielectric on the uncovered portions of the channel structures.

6 . The method of claim 1 , wherein the forming the initial stack of semiconductor layers comprises:
forming a first layer of a first dielectric material on a surface of a first semiconductor material over the substrate; forming an initial opening within the first layer, the initial opening uncovering the first semiconductor material; forming the sidewall structure within the initial opening such that the first semiconductor material is uncovered by an inner opening through the sidewall structure, the sidewall structure including a second dielectric material; and forming the initial stack of semiconductor layers within the inner opening.

7 . The method of claim 1 , wherein:
the S/D regions are formed on the uncovered side surfaces of the channel structures by epitaxial growth.

8 . A method of microfabrication, the method comprising:
forming an initial stack of semiconductor layers by epitaxial growth over a substrate, the initial stack of semiconductor layers comprising channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate, the channel structures comprising a first channel structure and a second channel structure positioned above the first channel structure, wherein the initial stack of semiconductor layers is surrounded by a sidewall structure; removing first portions of the sidewall structure to uncover first sides of the initial stack; forming source/drain (S/D) regions on uncovered side surfaces of the channel structures from the first sides of the initial stack; removing second portions of the sidewall structure to uncover second sides of the initial stack; and replacing the sacrificial gate layers with gate structures from the second sides of the initial stack, wherein the forming the S/D regions comprises: forming a protective structure to cover respective side surfaces of the second channel structure from the first sides of the initial stack; and forming first S/D regions of the S/D regions on respective side surfaces of the first channel structure.

9 . The method of claim 8 , further comprising:
depositing a first filler material to cover the respective side surfaces of the first channel structure from the first sides of the initial stack; forming the protective structure over the first filler material while leaving the first filler material partially uncovered; and selectively etching the first filler material to uncover the respective side surfaces of the first channel structure.

10 . The method of claim 9 , wherein the forming the protective structure comprises:
depositing a second filler material over the first filler material to cover the respective side surfaces of the second channel structure, wherein the first filler material and the second filler material are etch selective to each other; and directionally etching the second filler material to partially uncover the first filler material such that a remaining portion of the second filler material forms the protective structure.

11 . The method of claim 8 , further comprising:
removing the protective structure; and forming second S/D regions of the S/D regions on the respective side surfaces of the second channel structure.

12 . The method of claim 8 , further comprising:
forming indentations by removing end portions of the sacrificial gate layers from the first sides of the initial stack; and forming inner spacers in the indentations.

13 . The method of claim 8 , wherein the replacing the sacrificial gate layers with the gate structures comprises:
forming the gate structures all around respective channel structures.

14 . The method of claim 8 , wherein the replacing the sacrificial gate layers with the gate structures comprises:
forming at least one gate dielectric of the gate structures over uncovered portions of the channel structures; and forming at least one work function metal (WFM) of the gate structures over the at least one gate dielectric.

15 . The method of claim 14 , wherein the forming the at least one gate dielectric of the gate structures comprises:
selectively depositing the at least one dielectric on the uncovered portions of the channel structures.

16 . The method of claim 8 , wherein the forming the initial stack of semiconductor layers comprises:
forming a first layer of a first dielectric material on a surface of a first semiconductor material over the substrate; forming an initial opening within the first layer, the initial opening uncovering the first semiconductor material; forming the sidewall structure within the initial opening such that the first semiconductor material is uncovered by an inner opening through the sidewall structure, the sidewall structure including a second dielectric material; and forming the initial stack of semiconductor layers within the inner opening.

17 . A method of microfabrication, the method comprising:
forming an initial stack of semiconductor layers by epitaxial growth over a substrate, the initial stack of semiconductor layers comprising channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate, the channel structures comprising a first channel structure and a second channel structure positioned above the first channel structure, wherein the initial stack of semiconductor layers is surrounded by a sidewall structure; removing first portions of the sidewall structure to uncover first sides of the init

Assignees

• Tokyo Electron Ltd

Inventors

• Gardner Mark I
• Fulford H Jim
• Mukhopadhyay Partha

Classifications

• H10D88/01 Primary

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title