3D horizontal DRAM with in-situ bridge

Patent metadata

Field	Value
Publication number	US-12464703-B2
Application number	US-202217946690-A
Country	US
Kind code	B2
Filing date	Sep 16, 2022
Priority date	Feb 15, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate, wherein each DRAM cell unit comprises a respective transistor, a respective capacitor and a respective bridge structure, each bridge structure is configured to electrically couple the respective transistor to the respective capacitor, each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate and adjacent to and co-planar with the respective transistor in the horizontal direction, and each bridge structure comprises salicide material.

2 . The semiconductor device of claim 1 , wherein:
each bridge structure is configured to function as a respective source/drain (S/D) region of the respective transistor.

3 . The semiconductor device of claim 2 , wherein each transistor comprises:
a respective channel structure that is configured to have a current flow path in the horizontal direction, a respective gate structure all around the respective channel structure; and another respective S/D region positioned on an opposing end of the respective channel structure, relative to the respective bridge structure.

4 . The semiconductor device of claim 1 , wherein:
each bridge structure is configured to be electrically coupled to a respective inner conductor of the respective capacitor.

5 . The semiconductor device of claim 4 , wherein each capacitor comprises:
a respective capacitor dielectric all around the respective inner conductor; and a respective outer conductor all around the respective capacitor dielectric.

6 . The semiconductor device of claim 5 , wherein:
each outer conductor comprises metal material.

7 . The semiconductor device of claim 4 , wherein:
each inner conductor comprises doped semiconductor material.

8 . The semiconductor device of claim 7 , wherein:
each inner conductor comprises silicon, a respective channel structure of the respective transistor comprises silicon, and each inner conductor and the respective channel structure comprise different dopants.

9 . The semiconductor device of claim 1 , wherein:
each bridge structure comprises epitaxially grown material.

10 . The semiconductor device of claim 1 , wherein:
the stack of DRAM cell units includes a stack of transistors separated in the vertical direction by dielectric material.

11 . A method of manufacturing a semiconductor device, the method comprising:
forming a layer stack over a substrate, the layer stack including sub-stacks separated vertically from each other, wherein each sub-stack comprises a respective semiconductor layer positioned between respective dielectric layers; dividing the layer stack into a transistor region and a capacitor region; forming a respective transistor in each sub-stack in the transistor region; forming a respective capacitor in each sub-stack in the capacitor region, wherein each capacitor is elongated in a horizontal direction parallel to a working surface of the substrate and adjacent to and co-planar with the respective transistor in the horizontal direction; and forming a respective bridge structure that comprises salicide material and is configured to electrically couple each transistor to the respective capacitor.

12 . The method of claim 11 , wherein the dividing the layer stack comprises:
directionally etching each semiconductor layer to form a respective channel structure in the transistor region, wherein each channel structure is configured to have a current flow path in the horizontal direction.

13 . The method of claim 12 , wherein:
each bridge structure is formed on one end of the respective channel structure and configured to function as a respective source/drain (S/D) region.

14 . The method of claim 13 , wherein the forming the respective transistor comprises:
forming another respective source/drain (S/D) region on an opposing end of each channel structure, relative to the respective bridge structure; removing the respective dielectric layers in the transistor region to uncover each channel structure; and forming a respective gate structure all around each channel structure.

15 . The method of claim 11 , wherein the forming the respective capacitor comprises:
removing the respective dielectric layers in the capacitor region to uncover each semiconductor layer; and forming a respective inner conductor using each semiconductor layer in the capacitor region.

16 . The method of claim 15 , wherein:
forming the respective inner conductor comprises epitaxially growing a semiconductor material on each semiconductor layer in the capacitor region or doping each semiconductor layer in the capacitor region.

17 . The method of claim 15 , further comprising:
forming a respective capacitor dielectric all around each inner conductor; and forming a respective outer conductor all around each capacitor dielectric.

18 . The method of claim 11 , wherein:
each bridge structure is formed by epitaxial growth.

19 . The method of claim 11 , wherein:
each bridge structure is formed by salicidation.

20 . The method of claim 19 , wherein the salicidation comprises:
forming metal material between a respective channel structure of each transistor and a respective inner conductor of each capacitor; forming a respective metal silicide between each channel structure and the respective inner conductor; and removing remaining metal material.

Assignees

• Tokyo Electron Ltd

Inventors

• Gardner Mark I
• Fulford H Jim

Classifications

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title