Vertical transistors and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12457768-B2
Application number	US-202217749938-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	May 20, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a transistor structure comprising:
a metal structure extending along a vertical direction;
a gate dielectric layer having a least a first portion around the metal structure;
a channel layer having at least a first portion around the gate dielectric layer;
a first metal electrode disposed below the metal structure and in electrical contact with a first end of the first portion of the channel layer;
a second metal electrode disposed above the metal structure and in electrical contact with a second end of the first portion of the channel layer;
a third metal electrode disposed above and in electrical contact with the metal structure; and
a dielectric structure disposed between the metal structure and the first metal electrode.

2 . The semiconductor device of claim 1 , further comprising:
a second transistor structure laterally disposed next to the transistor structure and comprising:
a second metal structure extending along the vertical direction;
a second gate dielectric layer having a least a first portion around the second metal structure;
a second channel layer having a least a first portion around the second gate dielectric layer;
a fourth metal electrode disposed below the second metal structure and above the first metal structure, and in electrical contact with a first end of the first portion of the second channel layer;
a fifth metal electrode disposed above the second metal structure and in electrical contact with a second end of the first portion of the second channel layer;
a sixth metal structure disposed above and in electrical contact with the second metal structure; and
a second dielectric structure disposed between the second metal structure and the fourth metal electrode.

3 . The semiconductor device of claim 2 , wherein the channel layer and second channel layer have respectively different conductive types.

4 . The semiconductor device of claim 1 , wherein the first metal electrode is formed in a solid disk shape, and the second metal electrode is formed in a ring shape.

5 . The semiconductor device of claim 4 , wherein the second metal electrode extends around the third metal electrode.

6 . The semiconductor device of claim 1 , wherein the gate dielectric layer and the channel layer each further have a second portion disposed below the metal structure, and wherein the respective second portions of the gate dielectric layer and channel layer are further disposed below the dielectric structure.

7 . The semiconductor device of claim 1 , further comprising a dielectric liner at least laterally separating the dielectric structure from the gate dielectric layer.

8 . The semiconductor device of claim 1 , wherein the dielectric structure is a second portion of the gate dielectric layer that is surrounded by the first portion of the gate dielectric layer.

9 . The semiconductor device of claim 1 , wherein the channel layer further comprises:
a two-dimensional material around the gate dielectric layer; and a conductive oxide material around the two-dimensional material.

10 . The semiconductor device of claim 9 , wherein the two-dimensional material has a vertical portion and a horizontal portion, both of which are in physical contact with the conductive oxide material.

11 . The semiconductor device of claim 1 , wherein the channel layer essentially consists of a two-dimensional material around the gate dielectric layer.

12 . A semiconductor device, comprising:
a first transistor structure comprising:
a first metal structure extending along a vertical direction;
a first gate dielectric layer around the first metal structure;
a first channel layer around the first gate dielectric layer;
a first metal electrode disposed below and in electrical contact with the first channel layer;
a second metal electrode disposed above the first metal structure and in electrical contact with the first channel layer;
a third metal electrode surrounded by the second metal structure and in electrical contact with the first metal structure; and
a first dielectric structure configured to lift the first metal structure away from the first metal electrode; and
a second transistor structure laterally disposed next to the first transistor structure and comprising:
a second metal structure extending along the vertical direction;
a second gate dielectric layer around the second metal structure;
a second channel layer around the second gate dielectric layer;
a fourth metal electrode disposed below and in electrical contact with the second channel layer;
a fifth metal electrode disposed above the second metal structure and in electrical contact with the second channel layer;
a sixth metal electrode surrounded by the fifth metal structure and in electrical contact with the second metal structure; and
a second dielectric structure configured to lift the second metal structure away from the fourth metal electrode.

13 . The semiconductor device of claim 12 , wherein the first channel layer and second channel layer have respectively different conductive types.

14 . The semiconductor device of claim 12 , wherein the first transistor structure further comprises a first dielectric liner at least laterally separating the first dielectric structure from the first gate dielectric layer, and the second transistor structure further comprises a second dielectric liner at least laterally separating the second dielectric structure from the second gate dielectric layer.

15 . The semiconductor device of claim 12 , wherein
the first channel layer further comprises:
a first two-dimensional material around the first gate dielectric layer; and
a first conductive oxide material around the first two-dimensional material; and
the second channel layer further comprises:
a second two-dimensional material around the second gate dielectric layer; and
a second conductive oxide material around the second two-dimensional material.

16 . The semiconductor device of claim 12 , wherein
the first channel layer essentially consists of a first two-dimensional material; and the second channel layer essentially consists of a second two-dimensional material.

17 . A method for fabricating semiconductor devices, comprising:
forming a first metal electrode at a bottom of an opening of a dielectric layer; lining the opening with a channel layer, wherein the channel layer is in electrical contact with the first metal electrode; further lining the opening with a gate dielectric layer; forming a dielectric structure above a horizontal portion of the gate dielectric layer; forming a gate structure by filling a remaining portion of the opening with a metal material; forming a second metal electrode above the gate structure, wherein the second metal electrode is in electrical contact with the channel layer; and forming a third metal electrode surrounded by the second metal electrode, wherein the third metal electrode is in electrical contact with the gate structure.

18 . The method of claim 17 , wherein the step of lining the opening with a channel layer comprises:
depositing a conductive oxide material over the opening; etching horizontal portions of the conductive oxide material; and lining the opening with a two-dimensional material.

19 . The method of claim 17 , wherein the step of further lining the opening with a gate dielectric layer comprises:
depositing a first high-k dielectric material over the opening; depositing a

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I
• Mukhopadhyay Partha

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D48/362

  Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT] · CPC title

• H10D30/6728 Primary

  Vertical TFTs · CPC title

• H10D30/478

  the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body · CPC title