Methods for forming high performance three dimensionally stacked transistors based on dielectric nano sheets

Patent metadata

Field	Value
Publication number	US-12356706-B2
Application number	US-202117558442-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.

First claim

What is claimed is:

1. A method comprising:
forming a set of dielectric layers and a set of dielectric nano sheets above a substrate, each of the set of dielectric layers and each of the set of dielectric nano sheets extending parallel to the substrate, and each of the set of dielectric nano sheets interposed between corresponding two dielectric layers of the set of dielectric layers;
removing a portion of material from each side of each of the dielectric layers in the set of dielectric layers;
forming dielectric structures of a different dielectric material to each area created by the removing the portion of material;
removing respective end portions of the dielectric nano sheets to form indents, wherein each of the indents is recessed toward a corresponding one of the dielectric nano sheets from a corresponding pair of the dielectric structures; and
forming a first source/drain structure and a second source/drain structure, the first source/drain structure coupled to first ends of the set of dielectric nano sheets, and the second source/drain structure coupled to second ends of the set of dielectric nano sheets.

2. The method of claim 1 , further comprising:
removing the set of dielectric layers;
forming channel regions on the set of dielectric nano sheets;
forming gate dielectric regions on the channel regions; and
forming gate structures on the gate dielectric regions.

3. The method of claim 2 , wherein the channel regions include at least one of WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, or phosphorene.

4. The method of claim 2 , wherein removing the set of dielectric layers includes:
placing a photoresist mask to cover the first source/drain structure and the second source/drain structure, the photoresist mask having an opening that exposes the set of dielectric layers; and
etching the set of dielectric layers through the opening of the photoresist mask.

5. The method of claim 1 , wherein the set of dielectric layers is a first set of dielectric layers and the set of dielectric nano sheets is a first set of dielectric nano sheets, the method further comprising:
forming, a second set of dielectric layers and a second set of dielectric nano sheets above the first set of dielectric layers and the first set of dielectric nano sheets, each of the second set of dielectric layers and each of the second set of dielectric nano sheets extending along a first direction, the second set of dielectric layers and the second set of dielectric nano sheets stacked along a second direction, each of the second set of dielectric nano sheets interposed between corresponding two dielectric layers of the second set of dielectric layers; and
forming a third source/drain structure and a fourth source/drain structure, the third source/drain structure coupled to third ends of the second set of dielectric nano sheets, the fourth source/drain structure coupled to fourth ends of the second set of dielectric nano sheets, the third source/drain structure disposed above the first source/drain structure, the fourth source/drain structure disposed above the second source/drain structure.

6. The method of claim 5 , wherein the second set of dielectric layers and the second set of dielectric nano sheets are formed prior to forming the first source/drain structure, the second source/drain structure, the third source/drain structure, and the fourth source/drain structure.

7. The method of claim 5 , further comprising:
removing the first set of dielectric layers and the second set of dielectric layers, after forming the first source/drain structure, the second source/drain structure, the third source/drain structure, and the fourth source/drain structure;
forming channel regions on the first set of dielectric nano sheets and the second set of dielectric nano sheets, after removing the first set of dielectric layers and the second set of dielectric layers;
forming gate dielectric regions on the channel regions; and
forming gate structures on the gate dielectric regions.

8. The method of claim 7 , wherein removing the first set of dielectric layers and the second set of dielectric layers, forming the channel regions on the first set of dielectric nano sheets and the second set of dielectric nano sheets, forming the gate dielectric regions on the channel regions, and forming the gate structures on the gate dielectric regions are performed while a capping layer is above the first set of dielectric nano sheets and the second set of dielectric nano sheets, the channel regions formed on all exposed sides of the first and second sets of dielectric nano sheets, the gate dielectric regions formed on all exposed sides of the channels, and the gate structures formed on all exposed sides of the gate dielectric regions.

9. The method of claim 8 , wherein the gate structures formed on each of the first set of dielectric nano sheets extend between the dielectric nano sheets of the first set of dielectric nano sheets as part of a first gate all around (GAA) structure, and wherein the gate structures formed on each of the second set of dielectric nano sheets extend between the dielectric nano sheets of the second set of dielectric nano sheets as part of a second GAA structure.

10. The method of claim 1 , wherein forming the first source/drain structure and the second source/drain structure includes:
depositing metal in the indents in an area outside of the indents; and
removing a portion of the metal in the area outside of the indents.

11. The method of claim 1 , wherein forming the first source/drain structure and the second source/drain structure includes:
selectively growing metal in the indents, a portion of the metal extending out of the indents.

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Gardner Mark I

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title