Method for bonding substrates
US-2016358881-A1 · Dec 8, 2016 · US
Cleaning, e.g. oxide removal
Cleaning, e.g. oxide removal · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W72/01971 |
| Official title | {Cleaning, e.g. oxide removal} |
| Display label | Cleaning, e.g. oxide removal |
| Total patents | 303 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 34 |
| 2016 | 41 |
| 2017 | 38 |
| 2018 | 35 |
| 2019 | 35 |
| 2020 | 27 |
| 2021 | 28 |
| 2022 | 15 |
| 2023 | 19 |
| 2024 | 18 |
| 2025 | 10 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Chip packaging structures
US-2016336285-A1 · Nov 17, 2016 · US
Semiconductor device having solderable and bondable electrical contact pads
US-9496237-B2 · Nov 15, 2016 · US
Pretreatment method for photoresist wafer processing
US-9469912-B2 · Oct 18, 2016 · US
Integrated circuit package
US-9472515-B2 · Oct 18, 2016 · US
Conductive Line System and Process
US-2016293511-A1 · Oct 6, 2016 · US
Scalable package architecture and associated techniques and configurations
US-2016260690-A1 · Sep 8, 2016 · US
Manufacturing method for semiconductor devices
US-2016247772-A1 · Aug 25, 2016 · US
Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages
US-9425064-B2 · Aug 23, 2016 · US
Low alpha tin
US-9425164-B1 · Aug 23, 2016 · US
Reduced volume interconnect for three-dimensional chip stack
US-2016240501-A1 · Aug 18, 2016 · US
Packaging devices and methods of manufacture thereof
US-9418952-B2 · Aug 16, 2016 · US
Dual layer stack for contact formation
US-9401336-B2 · Jul 26, 2016 · US
Reduced volume interconnect for three-dimensional chip stack
US-2016211242-A1 · Jul 21, 2016 · US
Packaging devices and methods of manufacture thereof
US-9355978-B2 · May 31, 2016 · US
Method for wafer dicing and composition useful thereof
US-9328318-B2 · May 3, 2016 · US
Thermocompression for semiconductor chip assembly
US-9287230-B2 · Mar 15, 2016 · US
Manufacturing method for semiconductor devices
US-2016064343-A1 · Mar 3, 2016 · US
Substrate contact opening
US-9275964-B2 · Mar 1, 2016 · US
In situ chamber clean with inert hydrogen helium mixture during wafer process
US-9269562-B2 · Feb 23, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W72/01971?
- CPC H10W72/01971 is the Cooperative Patent Classification code for “Cleaning, e.g. oxide removal.”
- How many patents are filed under CPC H10W72/01971 (Cleaning, e.g. oxide removal)?
- Our database includes 303 publications tagged with this CPC code.
- Is patent activity under CPC H10W72/01971 growing?
- Publication counts under this code: 18 in 2024 vs 10 in 2025 (latest complete years).