Conductive Line System and Process

Patent metadata

Field	Value
Publication number	US-2016293511-A1
Application number	US-201615180372-A
Country	US
Kind code	A1
Filing date	Jun 13, 2016
Priority date	Mar 15, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a dielectric layer over a semiconductor substrate, the dielectric layer comprising:
a negative tone photosensitive polyimide material over the semiconductor substrate; and
a positive tone photosensitive polyimide material over the negative tone photosensitive polyimide material; and
a first opening in the dielectric layer, wherein the first opening comprises:
first sidewalls that comprise the positive tone photosensitive polyimide material; and
a planar bottom surface that comprises the negative tone photosensitive polyimide material, the planar bottom surface being planar along the length of the planar bottom surface; and
a second opening in the dielectric layer, wherein the second opening comprises:
second sidewalls that comprise the positive tone photosensitive polyimide material and the negative tone photosensitive polyimide material; and
a bottom of the second opening that comprises a conductive material.

2 . The semiconductor device of claim 1 , further comprising a third opening in the dielectric layer, wherein the third opening comprises:
third sidewalls that comprise the positive tone photosensitive polyimide material; and a planar bottom surface of the third opening that comprises the negative tone photosensitive polyimide material, the planar bottom surface of the third opening being planar along the length of the planar bottom surface of the third opening.

3 . The semiconductor device of claim 2 , wherein the first opening and the third opening have a pitch of less than about 5 μm.

4 . The semiconductor device of claim 1 , further comprising an external contact in electrical connection with the conductive material.

5 . The semiconductor device of claim 4 , further comprising a conductive material filling the second opening, wherein the external contact is in physical contact with the conductive material.

6 . The semiconductor device of claim 5 , wherein the conductive material further comprises:
a first seed layer; and a bulk conductive material over the first seed layer.

7 . The semiconductor device of claim 6 , wherein the bulk conductive material is copper.

8 . A semiconductor device comprising:
a first photosensitive polyimide layer over a substrate, wherein the first photosensitive polyimide layer is a negative tone photosensitive material; a second photosensitive polyimide layer over the substrate, wherein the second photosensitive polyimide layer is a positive tone photosensitive material; and a plurality of holes extending through the second photosensitive polyimide layer, wherein the plurality of holes further comprises:
a first subset of holes that has a first height; and
a second subset of holes that has a second height less than the first height, the first subset of holes extending through the first photosensitive polyimide layer to expose a conductive element.

9 . The semiconductor device of claim 8 , further comprising a first conductive material within the second subset of holes, the first conductive material being routing lines.

10 . The semiconductor device of claim 9 , further comprising a second conductive material within the first subset of holes, the second conductive material being a contact region separated from the routing lines.

11 . The semiconductor device of claim 10 , wherein the first conductive material comprises a first material and the second conductive material comprises the first material.

12 . The semiconductor device of claim 11 , wherein the first material comprises copper.

13 . The semiconductor device of claim 9 , wherein the first conductive material further comprises:
a first seed layer; and a bulk material over the first seed layer.

14 . The semiconductor device of claim 9 , wherein the second subset of holes has a pitch of less than about 5 μm.

15 . A semiconductor device comprising:
an external contact electrically connected to a contact pad over a semiconductor substrate; a first conductive material electrically connecting the external contact to the contact pad, the first conductive material extending through a first photosensitive polyimide material and a second photosensitive polyimide material to make physical contact with the contact pad, wherein the second photosensitive polyimide material is a negative tone photosensitive material located between the first photosensitive polyimide material and the semiconductor substrate, and wherein the first photosensitive polyimide material is a positive tone photosensitive material; and a second conductive material embedded within the first photosensitive polyimide material and having a first bottom surface facing both the second photosensitive polyimide material and the semiconductor substrate.

16 . The semiconductor device of claim 15 , wherein the first conductive material and the second conductive material are the same material.

17 . The semiconductor device of claim 16 , wherein the first conductive material and the second conductive material are copper.

18 . The semiconductor device of claim 15 , wherein the second conductive material forms a routing line.

19 . The semiconductor device of claim 15 , further comprising a third conductive material embedded within the first photosensitive polyimide material and having a second bottom surface facing both the second photosensitive polyimide material and the semiconductor substrate.

20 . The semiconductor device of claim 19 , wherein the second conductive material and the third conductive material have a pitch of no greater than about 5 μm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu Yi
• Kuo Hung-Jui
• Liu Chung-Shi

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title

• H10W72/01953

  by etching · CPC title