Scalable package architecture and associated techniques and configurations

Patent metadata

Field	Value
Publication number	US-2016260690-A1
Application number	US-201414654814-A
Country	US
Kind code	A1
Filing date	Jul 11, 2014
Priority date	Jul 11, 2014
Publication date	Sep 8, 2016
Grant date	—

Abstract

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

First claim

1 . An integrated circuit (IC) assembly comprising:
a package substrate having a first side and a second side disposed opposite to the first side; a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side.

2 . The IC assembly of claim 1 , wherein:
the terminating edge of the mold compound is substantially planar with the inactive side of the die.

3 . The IC assembly of claim 1 , further comprising:
the second die, wherein the second die is mounted on the first die in a flip-chip configuration.

4 . The IC assembly of claim 3 , wherein:
the first side of the package substrate generally defines a plane; and at least a portion of the second die extends farther in a direction that is parallel with the plane than the first die.

5 . The IC assembly of claim 4 , wherein the second die is mounted, at least in part, on the terminating edge of the mold compound.

6 . The IC assembly of claim 5 , further comprising:
an epoxy-based film disposed on the inactive side of the first die between the first die and the second die and further disposed on the terminating edge of the mold compound between the second die and the terminating edge of the mold compound.

7 . The IC assembly of claim 6 , wherein the second die has an active side coupled with the first die and an inactive side disposed opposite to the active side, the IC assembly further comprising:
an underfill material in direct contact with a sidewall of the second die between the active side and the inactive side of the second die and further in direct contact with the terminating edge of the mold compound.

8 . The IC assembly of claim 1 , further comprising:
one or more through-mold interconnects formed through the mold compound; and an integrated circuit (IC) device coupled with the first side of the package substrate through the one or more through-mold interconnects, wherein the first die and the second die are disposed between the first side of the package substrate and the IC device.

9 . The IC assembly of claim 8 , wherein:
the first die is a system-on-chip (SoC) die; the second die is a memory die; and the IC device is a memory package.

10 . A method comprising:
providing a package substrate having a first side and a second side disposed opposite to the first side; coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; and forming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side.

11 . The method of claim 10 , wherein:
the terminating edge of the mold compound is substantially planar with the inactive side of the die.

12 . The method of claim 10 , further comprising:
coupling the second die with the first die in a flip-chip configuration.

13 . The method of claim 12 , wherein:
the first side of the package substrate generally defines a plane; and at least a portion of the second die extends farther in a direction that is parallel with the plane than the first die.

14 . The method of claim 13 , wherein the second die is coupled with the terminating edge of the mold compound.

15 . The method of claim 14 , further comprising:
depositing an epoxy-based film such that the epoxy-based film is disposed on the inactive side of the first die between the first die and the second die and further disposed on the terminating edge of the mold compound between the second die and the terminating edge of the mold compound.

16 . The method of claim 15 , wherein the second die has an active side coupled with the first die and an inactive side disposed opposite to the active side, the method further comprising:
depositing an underfill material in direct contact with a sidewall of the second die between the active side and the inactive side of the second die and further in direct contact with the terminating edge of the mold compound.

17 . The method of claim 10 , further comprising:
forming one or more through-mold interconnects through the mold compound; and coupling an integrated circuit (IC) device with the first side of the package substrate through the one or more through-mold interconnects, wherein the first die and the second die are disposed between the first side of the package substrate and the IC device.

18 . The method of claim 17 , wherein:
the first die is a system-on-chip (SoC) die; the second die is a memory die; and the IC device is a memory package.

19 . A computing device comprising:
a circuit board; and an integrated circuit (IC) assembly coupled with the circuit board, the IC assembly comprising:
a package substrate having a first side and a second side disposed opposite to the first side;
a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; and
a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side.

20 . The computing device of claim 19 , wherein:
the computing device is a mobile computing device including one or more of a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Assignees

• Intel Corp

Inventors

• Ganesan Sanka
• Ziadeh Bassam
• Nimkar Nitesh

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title