Thermocompression for semiconductor chip assembly

Patent metadata

Field	Value
Publication number	US-9287230-B2
Application number	US-201414525340-A
Country	US
Kind code	B2
Filing date	Oct 28, 2014
Priority date	Nov 14, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate such that the underfill material envelopes both the deformed solder bumps and the substrate pads. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads based on a compression force causing the solder bumps to be deformed against the substrate pads and the semiconductor chip pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

First claim

What is claimed is:

1. A semiconductor chip assembly comprising:
a semiconductor chip having pads;
a substrate having pads aligned to receive the semiconductor chip, wherein at least one of the semiconductor chip pads and substrate pads have solder bumps, the solder bumps being deformed against the substrate pads and the semiconductor chip pads; and
an underfill material applied to fill a gap between the semiconductor chip and the substrate, wherein the underfill material envelopes both the deformed solder bumps and the substrate pads, the underfill material not penetrating between the deformed solder bumps, the semiconductor chip pads, and the substrate pads based on a compression force causing the solder bumps to be deformed against the substrate pads and the semiconductor chip pads, and
wherein at least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and
wherein at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

2. The assembly of claim 1 , wherein the semiconductor chip further comprises copper pillars extending from the semiconductor chip pads and the solder bumps are between the ends of the copper pillars and the substrate pads.

3. The assembly of claim 1 , wherein only the substrate comprises solder bumps.

4. The assembly of claim 1 , wherein only the semiconductor chip comprises solder bumps.

5. The assembly of claim 1 , wherein the semiconductor chip and substrate both comprise solder bumps.

6. The assembly of claim 5 , further comprising solder bumps on the substrate pads.

7. The assembly of claim 1 , wherein the semiconductor chip further comprises copper pillars extending from the semiconductor chip pads, the copper pillars being devoid of solder bumps, and the solder bumps are on the substrate.

8. The assembly of claim 1 , further comprising a cap to the semiconductor chip and the substrate.

Assignees

• IBM

Inventors

• Sylvestre Julien

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title